Last Updated (Monday, 07 June 2010 15:03)

Welcome!

This is the home page of the Flexible Design Methodologies for Application Specific Processors (FlexASP) project at the Department of Computer Systems (DCS) of Tampere University of Technology (TUT).  Currently, the project's main research focus is on the Transport Triggered Architectures, and on codesign toolset issues.

TTA-based Codesign Environment

As part of the project we are developing a codesign toolset using TTA as the architecture template. The toolset is called TTA-based Codesign Environment (TCE).

TCE is a toolset for designing application-specific processors (ASP) based on the Transport triggered architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

TCE has been developed internally in the Tampere University of Technology since the early 2003. The current source code base consists of roughly 400 000 lines of C++ code.

Current status (updated on 2010-06-07)

Features implemented in TCE 1.2:

  • Compiler:
    • LLVM 2.7 based, Clang as the default frontend
    • Basic block instruction scheduler
    • Delay slot filling
    • Software bypassing
    • Custom operation support
    • Parallel TTA assembler
    • Software and hardware floating point support
  • Simulator:
    • Graphical and command line user interfaces
    • Interpretive debugging engine for cycle stepping
    • Static compiled engine for fast simulation with basic block granularity (but cycle count accuracy)
    • Dynamic compiled engine for improved startup time with fast simulation
  • Processor and Program Image Generation:
    • Support for generating implementation for the designed processor as VHDL
    • Generates bit image of the program (supported formats include the Altera MIF)
    • Dictionary-based instruction compression
  • Design space exploration:
    • Automated, manual and semi-automatic algorithm implementations
    • Tools that allow easy modification of the target architecture
    • Simple cost estimator for estimating area, power and delay
  • Integrated Development Environment tools:
    • Graphical user interface (GUI) for editing architecture resources
    • GUI for editing operation set definitions