Welcome!

This is the home page of the Flexible Design Methodologies for Application Specific Processors (FlexASP) project at the Department of Computer Systems (DCS) of Tampere University of Technology (TUT). Currently, the project's main research focus is on the Transport Triggered Architectures, and on codesign toolset issues.

News and updates

May 12th, 2012: ASILOMAR '11 publication added

We presented a paper about our operation description format and compiler retargeting:

  • Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala
    "Operation Set Customization in Retargetable Compilers".
    Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 6-9 Nov 2011, Pacific Grove, California (IEEEexplore)

December 13th, 2011: TCE 1.5 released

A new version of the toolset is now available for download.

This release includes support for LLVM 3.0, experimental OpenCL C Embedded Profile support (in offline compilation/standalone mode), a light weight (debug output) printing library, support for calling custom operations in specific function units, generalizations to the architecture description format to allow using the instruction scheduler for operation triggered architectures (with a proof of concept for the Cell SPU), several code generator improvements and plenty of bug fixes. See the CHANGES file for a more thorough change listing.

November 4th, 2011: SoC'11 publications added

We presented two new papers related to TCE in the SoC 2011 conference:

  • Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala,
    "Customizable Datapath Integrated Lock Unit,"
  • Vladimír Guzma, Teemu Pitkänen, Jarmo Takala,
    "Effects of Loop Unrolling and Use of Instruction Buffer on Processor Energy Consumption,"
    in Proc. of International Symposium on System on Chip 2011, Tampere, Finland, October 31-November 2, 2011

October 19th, 2011: Portable OpenCL (pocl) released

The work started in early 2009 as an experiment to schedule OpenCL C kernels for standalone application-specific processors has been now generalized and released as a separate open source project called Portable OpenCL (pocl).

(older news here)

About TTA-based Co-design Environment

As part of the project we are developing a codesign toolset using TTA as the architecture template. The toolset is called TTA-based Co-design Environment (TCE).

TCE is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

TCE has been developed in the Tampere University of Technology since the early 2003.

Further reading: LLVM project blog post about TCE.

Current status (updated on 2011-12-14)

Features in TCE 1.5: