TTA-based Co-design Environment (TCE) is a toolset for designing and programming customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
News and updates
February 27th, 2014: New research group name
The research group in Tampere University of Technology maintaining TCE was renamed from FlexASP to Customized Parallel Computing (CPC).
January 27th, 2014: TCE 1.9 released
A new version of the toolset is now available for download.
See the release announcement for details.
October 28th, 2013: new publications from Oulu added
A bunch of publications from University of Oulu that use TCE added.
October 17th, 2013: new publications added
New publications added:
Tomasz Patyk, David Guevorkian, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
"Low-Power Application-Specific FFT Processor for LTE Applications",
in SAMOS XIII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2013). (doi)
Heikki Kultala, Otto Esko, XianJun Jiao, Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Tommi Zetterman, Heikki Berg:
"Turbo Decoding on Tailored OpenCL Processor",
in IWCMC 2013: International Wireless Communications & Mobile Computing Conference (Cagliari, Italy, July 2013). (doi)
Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
"Design Methodology for Offloading Software Executions to FPGA",
in Journal of Signal Processing Systems, November 2011, vol. 65, issue 2. (doi)
About TTA-based Co-design Environment
As part of the project we are developing a codesign toolset using TTA as the architecture template. The toolset is called TTA-based Co-design Environment (TCE).
TCE is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
TCE has been developed in the Tampere University of Technology since the early 2003.
Further reading: LLVM project blog post about TCE.
Current status (updated on 2014-01)
Features in TCE 1.9:
- LLVM 3.4 based, Clang as the default frontend
- OpenCL support via the pocl project
- Basic block instruction scheduler (top-down and bottom-up)
- Delay slot filling
- Software bypassing
- (experimental) Operand sharing
- Custom operation support
- Parallel TTA assembler
- Software and hardware floating point support
- Basic debugging info support
- Multiple address space support
- Support for native computation on half precision floats (fp16)
- Graphical and command line user interfaces
- Interpretive debugging engine for cycle stepping
- Static compiled engine for fast simulation with basic block granularity (but cycle count accuracy)
- Dynamic compiled engine for improved startup time with fast simulation
- SystemC integration API
- Processor and Program Image Generation:
- Support for generating implementation for the designed processor as VHDL. Experimental support for Verilog.
- Generates bit image of the program (supported formats include the Altera MIF)
- Dictionary-based instruction compression
- Automated generation of the files needed to integrate the core to different FPGA platforms.
- IP-XACT 1.5 support
- Design space exploration:
- Automated, manual and semi-automatic algorithm implementations
- Tools that allow easy modification of the target architecture
- Automated search of the connectivity design space
- Integrated Development Environment tools:
- Graphical user interface (GUI) for editing architecture resources
- GUI for editing operation set definitions