TTA-based Co-design Environment (TCE) is a toolset for designing and programming customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

TCE development is directed by the Customized Parallel Computing (CPC) group at the Department of Pervasive Computing of Tampere University of Technology (TUT), Finland.

News and updates

September 23rd, 2014: new publications and theses added

  • Jääskeläinen Pekka, Kultala Heikki, Viitanen Timo, Takala Jarmo:
    "Code Density and Energy Efficiency of Exposed Datapath Architectures",
    in Journal of Signal Processing Systems July 2014 (download).
  • Helkala Janne, Viitanen Timo, Kultala Heikki, Jääskeläinen Pekka, Takala Jarmo, Zetterman Tommi, Berg Heikki:
    "Variable Length Instruction Compression on Transport Triggered Architectures",
    in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014 (download).
  • Rister B., Jääskeläinen P., Silven O., Hannuksela J.:
    "Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding",
    in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
  • Yviquel H., Sanchez A., Jääskeläinen P., Takala J.:
    "Efficient software synthesis of dynamic dataflow programs",
    in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
  • Master's thesis of Janne Helkala:
    Variable Length Instruction Compression on Transport Triggered Architectures (June, 2014) (link)
  • Master's thesis of Mikko Järvelä:
    Vector Operation Support for Transport Triggered Architectures (June, 2014) (link)

September 5th, 2014: TCE 1.10 released

A new version of the toolset is now available for download.

See the release announcement for details.

February 27th, 2014: New research group name

The research group in Tampere University of Technology maintaining TCE was renamed from FlexASP to Customized Parallel Computing (CPC).

January 27th, 2014: TCE 1.9 released

A new version of the toolset is now available for download.

See the release announcement for details.

October 28th, 2013: new publications from Oulu added

A bunch of publications from University of Oulu that use TCE added.

October 17th, 2013: new publications added

New publications added:

  • Tomasz Patyk, David Guevorkian, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
    "Low-Power Application-Specific FFT Processor for LTE Applications",
    in SAMOS XIII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2013). (doi)
  • Heikki Kultala, Otto Esko, XianJun Jiao, Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Tommi Zetterman, Heikki Berg:
    "Turbo Decoding on Tailored OpenCL Processor",
    in IWCMC 2013: International Wireless Communications & Mobile Computing Conference (Cagliari, Italy, July 2013). (doi)
  • Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
    "Design Methodology for Offloading Software Executions to FPGA",
    in Journal of Signal Processing Systems, November 2011, vol. 65, issue 2. (doi)
(older news here)

About TTA-based Co-design Environment

As part of the project we are developing a codesign toolset using TTA as the architecture template. The toolset is called TTA-based Co-design Environment (TCE).

TCE is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

TCE has been developed in the Tampere University of Technology since the early 2003.

Further reading: LLVM project blog post about TCE.

Current status (updated on 2014-01)

Features in TCE 1.9: