OpenASIP  2.0
AlteraOnchipRamGenerator.cc
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1 /*
2  Copyright (c) 2002-2010 Tampere University.
3 
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24 /**
25  * @file AlteraOnchipRamGenerator.cc
26  *
27  * Implementation of AlteraOnchipRamGenerator class.
28  *
29  * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30  * @note rating: red
31  */
32 
33 #include <iostream>
34 #include <vector>
36 #include "Netlist.hh"
37 #include "HDLPort.hh"
38 using std::endl;
39 
41  "altera_onchip_ram_comp.vhd";
42 
44  int memMauWidth,
45  int widthInMaus,
46  int addrWidth,
47  TCEString initFile,
48  const PlatformIntegrator* integrator,
49  std::ostream& warningStream,
50  std::ostream& errorStream):
51  AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
52  integrator, warningStream, errorStream) {
53 
54  bool inverted = true;
55  bool noInvert = false;
56  TCEString byteEnableWidth;
57  byteEnableWidth << DATAW_G << "/8";
58  addPort("dmem_data_in",
59  new HDLPort("q", DATAW_G,
60  ProGe::BIT_VECTOR, ProGe::OUT, noInvert,
61  memoryTotalWidth()));
62  addPort("dmem_data_out",
63  new HDLPort("data", DATAW_G,
64  ProGe::BIT_VECTOR, ProGe::IN, noInvert,
65  memoryTotalWidth()));
66  addPort("dmem_addr",
67  new HDLPort("address", ADDRW_G,
68  ProGe::BIT_VECTOR, ProGe::IN, noInvert,
69  memoryAddrWidth()));
70  addPort("dmem_mem_en_x",
71  new HDLPort("clken", "1", ProGe::BIT, ProGe::IN, inverted, 1));
72  addPort("dmem_wr_en_x",
73  new HDLPort("wren", "1", ProGe::BIT, ProGe::IN, inverted, 1));
74  addPort("dmem_bytemask",
75  new HDLPort("byteena", byteEnableWidth, ProGe::BIT_VECTOR,
76  ProGe::IN, noInvert, memoryWidthInMaus()));
77  addPort("clk",
78  new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
79 }
80 
82 }
83 
84 bool
86  return true;
87 }
88 
89 
90 std::vector<TCEString>
92 
93  return instantiateAlteraTemplate(COMPONENT_FILE, outputPath);
94 }
95 
96 
99 
100  return ttaCoreName() + "_altera_onchip_ram_comp";
101 }
102 
103 
104 TCEString
105 AlteraOnchipRamGenerator::instanceName(int coreId, int memIndex) const {
106 
107  TCEString iname("onchip_dmem_");
108  return iname << memoryIndexString(coreId, memIndex);
109 }
110 
AlteraMemGenerator::ADDRW_G
static const TCEString ADDRW_G
Definition: AlteraMemGenerator.hh:77
Netlist.hh
AlteraMemGenerator::DATAW_G
static const TCEString DATAW_G
Definition: AlteraMemGenerator.hh:78
AlteraMemGenerator
Definition: AlteraMemGenerator.hh:43
MemoryGenerator::addPort
void addPort(const TCEString &name, HDLPort *port)
Definition: MemoryGenerator.cc:294
HDLPort
Definition: PlatformIntegrator/HDLPort.hh:48
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
MemoryGenerator::ttaCoreName
TCEString ttaCoreName() const
Definition: MemoryGenerator.cc:319
MemoryGenerator::memoryIndexString
TCEString memoryIndexString(int coreId, int memIndex) const
Definition: MemoryGenerator.cc:383
AlteraOnchipRamGenerator::moduleName
virtual TCEString moduleName() const
Definition: AlteraOnchipRamGenerator.cc:98
AlteraOnchipRamGenerator::~AlteraOnchipRamGenerator
virtual ~AlteraOnchipRamGenerator()
Definition: AlteraOnchipRamGenerator.cc:81
HDLPort.hh
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
AlteraOnchipRamGenerator::instanceName
virtual TCEString instanceName(int coreId, int memIndex) const
Definition: AlteraOnchipRamGenerator.cc:105
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
AlteraOnchipRamGenerator::COMPONENT_FILE
static const TCEString COMPONENT_FILE
Definition: AlteraOnchipRamGenerator.hh:70
AlteraMemGenerator::instantiateAlteraTemplate
std::vector< TCEString > instantiateAlteraTemplate(const TCEString &templateFile, const TCEString &outputPath) const
Definition: AlteraMemGenerator.cc:62
MemoryGenerator::memoryWidthInMaus
int memoryWidthInMaus() const
Definition: MemoryGenerator.cc:205
TCEString
Definition: TCEString.hh:53
AlteraOnchipRamGenerator::AlteraOnchipRamGenerator
AlteraOnchipRamGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
Definition: AlteraOnchipRamGenerator.cc:43
PlatformIntegrator
Definition: PlatformIntegrator.hh:65
AlteraOnchipRamGenerator::generatesComponentHdlFile
virtual bool generatesComponentHdlFile() const
Definition: AlteraOnchipRamGenerator.cc:85
MemoryGenerator::memoryTotalWidth
int memoryTotalWidth() const
Definition: MemoryGenerator.cc:193
MemoryGenerator::memoryAddrWidth
int memoryAddrWidth() const
Definition: MemoryGenerator.cc:212
AlteraOnchipRamGenerator::generateComponentFile
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
Definition: AlteraOnchipRamGenerator.cc:91
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
AlteraOnchipRamGenerator.hh