OpenASIP  2.0
Stratix2SramGenerator.cc
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1 /*
2  Copyright (c) 2002-2010 Tampere University.
3 
4  This file is part of TTA-Based Codesign Environment (TCE).
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24 /**
25  * @file Stratix2SramGenerator.cc
26  *
27  * Implementation of Stratix2SramGenerator class.
28  *
29  * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30  * @note rating: red
31  */
32 
33 #include <iostream>
34 #include <vector>
35 #include "StringTools.hh"
36 #include "PlatformIntegrator.hh"
37 #include "MemoryGenerator.hh"
38 #include "Stratix2SramGenerator.hh"
39 #include "Netlist.hh"
40 #include "NetlistBlock.hh"
41 #include "NetlistPort.hh"
42 #include "HDLPort.hh"
43 using std::vector;
44 using std::endl;
46 using ProGe::NetlistPort;
47 
49  int memMauWidth,
50  int widthInMaus,
51  int addrWidth,
52  TCEString initFile,
53  const PlatformIntegrator* integrator,
54  std::ostream& warningStream,
55  std::ostream& errorStream) :
56  MemoryGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
57  integrator, warningStream, errorStream) {
58 
59  ProGe::Parameter dataw("sram_dataw", "integer", "32");
60  ProGe::Parameter addrw("sram_addrw", "integer", "18");
61  addParameter(dataw);
62  addParameter(addrw);
63  addPort("STRATIXII_SRAM_DQ",
64  new HDLPort("STRATIXII_SRAM_DQ", "sram_dataw", ProGe::BIT_VECTOR,
65  ProGe::BIDIR, false, 32));
66  addPort("STRATIXII_SRAM_ADDR",
67  new HDLPort("STRATIXII_SRAM_ADDR", "sram_addrw",
68  ProGe::BIT_VECTOR, ProGe::OUT, false, 18));
69  addPort("STRATIXII_SRAM_WE_N",
70  new HDLPort("STRATIXII_SRAM_WE_N", "1", ProGe::BIT_VECTOR,
71  ProGe::OUT, false, 1));
72  addPort("STRATIXII_SRAM_OE_N",
73  new HDLPort("STRATIXII_SRAM_OE_N", "1", ProGe::BIT_VECTOR,
74  ProGe::OUT, false, 1));
75  addPort("STRATIXII_SRAM_CS_N",
76  new HDLPort("STRATIXII_SRAM_CS_N", "1", ProGe::BIT_VECTOR,
77  ProGe::OUT, false, 1));
78  addPort("STRATIXII_SRAM_BE_N0",
79  new HDLPort("STRATIXII_SRAM_BE_N0", "1", ProGe::BIT_VECTOR,
80  ProGe::OUT, false, 1));
81  addPort("STRATIXII_SRAM_BE_N1",
82  new HDLPort("STRATIXII_SRAM_BE_N1", "1", ProGe::BIT_VECTOR,
83  ProGe::OUT, false, 1));
84  addPort("STRATIXII_SRAM_BE_N2",
85  new HDLPort("STRATIXII_SRAM_BE_N2", "1", ProGe::BIT_VECTOR,
86  ProGe::OUT, false, 1));
87  addPort("STRATIXII_SRAM_BE_N3",
88  new HDLPort("STRATIXII_SRAM_BE_N3", "1", ProGe::BIT_VECTOR,
89  ProGe::OUT, false, 1));
90 }
91 
92 
94 }
95 
96 
97 void
99  const ProGe::NetlistBlock& ttaCore,
100  ProGe::NetlistBlock& integratorBlock,
101  int /*memIndex*/,
102  int coreId) {
103 
104  for (int i = 0; i < parameterCount(); i++) {
105  integratorBlock.setParameter(
106  parameter(i).name(),
107  parameter(i).type(),
108  parameter(i).value());
109  }
110 
111  for (int i = 0; i < portCount(); i++) {
112  const HDLPort* hdlPort = port(i);
113  NetlistPort* memPort = hdlPort->convertToNetlistPort(integratorBlock);
114 
116  const NetlistPort* corePort = ttaCore.port(corePortName);
117  assert(corePort != NULL);
118 
120  integratorBlock, *memPort, *corePort,
121  hdlPort->needsInversion(), coreId);
122  }
123 
124 }
125 
126 bool
128 
129  // Sram controller is integrated into the lsu itself
130  // No need to generate separate file
131  return false;
132 }
133 
134 std::vector<TCEString>
136 
137  vector<TCEString> noFileToGenerate;
138  return noFileToGenerate;
139 }
140 
141 
142 TCEString
144 
145  return "stratixII_sram_comp";
146 }
147 
148 
149 TCEString
150 Stratix2SramGenerator::instanceName(int coreId, int memIndex) const {
151 
152  TCEString iname("stratixII_sram_");
153  return iname << memoryIndexString(coreId, memIndex);
154 }
Netlist.hh
MemoryGenerator::port
const HDLPort * port(int index) const
Definition: MemoryGenerator.cc:249
Stratix2SramGenerator::instanceName
virtual TCEString instanceName(int coreId, int memIndex) const
Definition: Stratix2SramGenerator.cc:150
ProGe::NetlistBlock
Definition: NetlistBlock.hh:61
MemoryGenerator::addPort
void addPort(const TCEString &name, HDLPort *port)
Definition: MemoryGenerator.cc:294
HDLPort
Definition: PlatformIntegrator/HDLPort.hh:48
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
ProGe::Parameter::type
const TCEString & type() const
Definition: Parameter.cc:138
MemoryGenerator.hh
ProGe::NetlistBlock::setParameter
void setParameter(const std::string &name, const std::string &type, const std::string &value)
Definition: NetlistBlock.cc:89
ProGe::BIDIR
@ BIDIR
Bidirectional port.
Definition: ProGeTypes.hh:55
MemoryGenerator::memoryIndexString
TCEString memoryIndexString(int coreId, int memIndex) const
Definition: MemoryGenerator.cc:383
HDLPort::convertToNetlistPort
ProGe::NetlistPort * convertToNetlistPort(ProGe::NetlistBlock &block) const
Definition: HDLPort.cc:127
Stratix2SramGenerator::~Stratix2SramGenerator
virtual ~Stratix2SramGenerator()
Definition: Stratix2SramGenerator.cc:93
StringTools.hh
assert
#define assert(condition)
Definition: Application.hh:86
MemoryGenerator::parameter
const ProGe::Parameter & parameter(int index) const
Definition: MemoryGenerator.cc:308
ProGe::Parameter
Definition: Parameter.hh:62
NetlistPort.hh
ProGe::Parameter::name
const TCEString & name() const
Definition: Parameter.cc:133
NetlistBlock.hh
ProGe::Parameter::value
const TCEString & value() const
Definition: Parameter.cc:143
HDLPort.hh
Stratix2SramGenerator::generateComponentFile
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
Definition: Stratix2SramGenerator.cc:135
Stratix2SramGenerator::Stratix2SramGenerator
Stratix2SramGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
Definition: Stratix2SramGenerator.cc:48
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
Stratix2SramGenerator.hh
MemoryGenerator::corePortName
TCEString corePortName(const TCEString &portBaseName, int coreId) const
Definition: MemoryGenerator.cc:356
MemoryGenerator::connectPorts
virtual void connectPorts(ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
Definition: MemoryGenerator.cc:392
MemoryGenerator::portCount
int portCount() const
Definition: MemoryGenerator.cc:243
TCEString
Definition: TCEString.hh:53
PlatformIntegrator.hh
MemoryGenerator::addParameter
void addParameter(const ProGe::Parameter &add)
Definition: MemoryGenerator.cc:313
ProGe::NetlistPort
Definition: NetlistPort.hh:70
PlatformIntegrator
Definition: PlatformIntegrator.hh:65
MemoryGenerator::portKeyName
TCEString portKeyName(const HDLPort *port) const
Definition: MemoryGenerator.cc:275
Stratix2SramGenerator::addMemory
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
Definition: Stratix2SramGenerator.cc:98
Stratix2SramGenerator::moduleName
virtual TCEString moduleName() const
Definition: Stratix2SramGenerator.cc:143
MemoryGenerator::parameterCount
int parameterCount() const
Definition: MemoryGenerator.cc:302
ProGe::NetlistBlock::port
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
Definition: NetlistBlock.cc:97
Stratix2SramGenerator::generatesComponentHdlFile
virtual bool generatesComponentHdlFile() const
Definition: Stratix2SramGenerator.cc:127
MemoryGenerator
Definition: MemoryGenerator.hh:85
HDLPort::needsInversion
bool needsInversion() const
Definition: HDLPort.cc:122