OpenASIP  2.0
VerilogNetlistWriter.cc
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1 /*
2  Copyright (c) 2012 Vinogradov Viacheslav.
3 
4  This file is going to be a part of TTA-Based Codesign Environment (TCE).
5 
6  Permission is hereby granted, free of charge, to any person obtaining a
7  copy of this software and associated documentation files (the "Software"),
8  to deal in the Software without restriction, including without limitation
9  the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  and/or sell copies of the Software, and to permit persons to whom the
11  Software is furnished to do so, subject to the following conditions:
12 
13  The above copyright notice and this permission notice shall be included in
14  all copies or substantial portions of the Software.
15 
16  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  DEALINGS IN THE SOFTWARE.
23  */
24 /**
25  * @file VerilogNetlistWriter.cc
26  *
27  * Implementation of VerilogNetlistWriter class based on VHDLNetlistWriter.cc
28  *
29  * @author Vinogradov Viacheslav 2012
30  * @note rating: red
31  */
32 
33 #include <iostream>
34 #include <fstream>
35 #include <string>
36 #include <set>
37 #include <cctype>
38 #include <algorithm>
39 
40 #include "VerilogNetlistWriter.hh"
41 #include "Netlist.hh"
42 #include "NetlistBlock.hh"
43 #include "NetlistPort.hh"
44 #include "Parameter.hh"
45 
46 #include "FileSystem.hh"
47 #include "Conversion.hh"
48 #include "ContainerTools.hh"
49 #include "AssocTools.hh"
50 #include "StringTools.hh"
51 
52 using std::string;
53 using std::endl;
54 using std::ofstream;
55 using std::set;
56 using std::pair;
57 
58 const std::string GROUND_SIGNAL = "ground_signal";
59 const std::string PARAM_STRING = "string";
60 
61 namespace ProGe {
62 
63 /**
64  * Constructor. Records the input netlist for which it can generate Verilog.
65  *
66  * @param netlist The input netlist.
67  */
69  const BaseNetlistBlock& targetBlock)
70  : NetlistWriter(targetBlock), groundWidth_(0) {}
71 
72 /**
73  * The destructor.
74  */
76 }
77 
78 /**
79  * Generates the Verilog files and writes them to the given directory.
80  *
81  * @param dstDirectory The destination directory.
82  * @exception IOException If an IO error occurs.
83  * @exception InvalidData If the netlist is invalid.
84  */
85 void
86 VerilogNetlistWriter::write(const std::string& dstDirectory) {
87  const BaseNetlistBlock& block = this->targetNetlistBlock();
88  if (block.netlist().isEmpty()) {
89  string errorMsg = "Empty input netlist block.";
90  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
91  }
92 
93  writeNetlistParameterPackage(dstDirectory);
94  writeBlock(block, dstDirectory);
95 }
96 
97 /**
98  * Writes the package(include files for verilog) that defines parameters of
99  * the netlist.
100  *
101  * @param dstDirectory The destination directory.
102  */
103 void
105  const std::string& dstDirectory) const {
106  string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
107  netlistParameterPkgName() + "_pkg.vh";
108  ofstream outFile;
109  outFile.open(fileName.c_str(), ofstream::out);
110  for (size_t i = 0; i < targetNetlistBlock().netlist().parameterCount();
111  i++) {
113  outFile << "parameter " << param.name() << " = " << param.value();
114  if (i != targetNetlistBlock().netlist().parameterCount() - 1)
115  outFile << ",";
116  outFile << endl;
117  }
118 }
119 
120 /**
121  * Returns the name of the netlist parameter package(include file).
122  *
123  * @return The name.
124  */
125 std::string
127  return targetNetlistBlock().moduleName() + "_params";
128 }
129 
130 
131 /**
132  * Writes the given block of the netlist to the given destination directory.
133  *
134  * @param block The netlist block.
135  * @param dstDirectory The destination directory.
136  * @exception IOException If the file cannot be created.
137  */
138 void
140  const BaseNetlistBlock& block, const std::string& dstDirectory) {
141  string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
142  block.moduleName() + ".v";
143  if (!FileSystem::fileIsCreatable(fileName) &&
144  !(FileSystem::fileExists(fileName) &&
145  FileSystem::fileIsWritable(fileName))) {
146 
147  string errorMsg = "Unable to create file: " + fileName;
148  throw IOException(__FILE__, __LINE__, __func__, errorMsg);
149  }
150 
151  const string entityName = block.moduleName();
152 
153  ofstream outFile;
154  outFile.open(fileName.c_str(), ofstream::out);
155 
156  // create module
157  outFile << "module " + entityName << endl;
158 
159  //create include
160  string separator;
161  outFile << "#(" << endl;
162  if (block.netlist().parameterCount() > 0) {
163  outFile << "`include \"" << netlistParameterPkgName() << "_pkg.vh\""
164  << endl;
165  separator = ",";
166  }
167 
168  for (size_t i = 0; i < block.packageCount(); i++) {
169  outFile << separator << endl;
170  outFile << "`include \"" << block.package(i) << "_pkg.vh\"" << endl;
171  separator = ",";
172  }
173 
174  outFile << ")" << endl;
175 
176  // create port declarations
177  writePortDeclaration(block, 1, indentation(1), outFile);
178  outFile << endl;
179 
180  // create generics
181  writeGenericDeclaration(block, 1, indentation(1), outFile);
182  // create architecture
183  writeSignalDeclarations(block, outFile);
184  outFile << endl;
185  writeSignalAssignments(block, outFile);
186  outFile << endl;
187  writePortMappings(block, outFile);
188  outFile << "endmodule" << endl;
189  outFile << endl;
190  outFile.close();
191 }
192 
193 /**
194  * Writes the generic(parameter) declarations of the given netlist block.
195  *
196  * @param block The netlist block.
197  * @param indentationLevel The indentation level where the generic declaration
198  * is written.
199  * @param indentation The string used as indentation (one level).
200  * @param stream The stream to write.
201  */
202 void
204  const BaseNetlistBlock& block, unsigned int indentationLevel,
205  const std::string& indentation, std::ostream& stream) {
206  if (block.parameterCount() > 0) {
207  stream << endl;
208  for (size_t i = 0; i < block.parameterCount(); i++) {
209  stream << generateIndentation(indentationLevel, indentation)
210  << "parameter ";
211  Parameter param = block.parameter(i);
212  stream << generateIndentation(indentationLevel + 1, indentation)
213  << param.name();
214  if (param.defaultValue() != "") {
215  stream << " = ";
216  if (param.type().lower() == PARAM_STRING) {
217  // string literal needs quot. marks
218  if (!param.defaultValue().startsWith("\""))
219  stream << "\"";
220  stream << param.defaultValue();
221  if (!param.defaultValue().endsWith("\"")) stream << "\"";
222  } else {
223  stream << param.defaultValue();
224  }
225  }
226  stream << ";" << endl;
227  }
228  }
229 }
230 
231 /**
232  * Writes the port declaration of the given netlist block.
233  *
234  * @param block The netlist block.
235  * @param indentationLevel The indentation level where the generic declaration
236  * is written.
237  * @param indentation The string used as indentation (one level).
238  * @param stream The stream to write.
239  */
240 void
242  const BaseNetlistBlock& block, unsigned int indentationLevel,
243  const std::string& indentation, std::ostream& stream) {
244  stream << generateIndentation(indentationLevel, indentation) << "("
245  << endl;
246 
247  for (size_t i = 0; i < block.portCount(); i++) {
248  const NetlistPort& port = block.port(i);
249  string portName = port.name();
250  string direction = directionString(port.direction());
251  stream << generateIndentation(indentationLevel+1, indentation)
252  << direction;
253 
254  if (port.dataType() == BIT) {
255  //nothing to do
256  } else {
257  stream << "[";
258  // zero width ports as (0: 0
259  if (isNumber(port.widthFormula()) &&
260  Conversion::toInt(port.widthFormula()) == 0) {
261  stream << "0";
262  } else if (isNumber(port.widthFormula())) {
263  stream << Conversion::toInt(port.widthFormula()) - 1;
264  } else {
265  stream << port.widthFormula() << "-1";
266  }
267  stream << ":0]";
268  }
269  stream << " " << portName;
270  if (i + 1 == block.portCount()) {
271  stream << ");";
272  } else {
273  stream << ",";
274  }
275  stream << endl;
276  }
277 }
278 
279 /**
280  * Writes the Verilog signal declarations to the given stream.
281  *
282  * @param block The block of which the signals are written.
283  * @param stream The stream to write.
284  */
285 void
287  const BaseNetlistBlock& block, std::ofstream& stream) {
288  // collect all the sub blocks to a set
289  typedef std::set<const BaseNetlistBlock*, NetlistBlockNameComparator>
290  BlockSet;
291  BlockSet subBlocks;
292  for (size_t i = 0; i < block.subBlockCount(); i++) {
293  // ports belonging to virtual blocks have static values, thus they are
294  // excluded
295  if (!block.subBlock(i).isVirtual()) {
296  subBlocks.insert(&block.subBlock(i));
297  }
298  }
299 
300  // create a signal for each port in the sub-blocks
301  for (BlockSet::const_iterator iter = subBlocks.begin();
302  iter != subBlocks.end(); iter++) {
303  const BaseNetlistBlock* subBlock = *iter;
304 
305  for (size_t i = 0; i < subBlock->portCount(); i++) {
306  const NetlistPort& port = subBlock->port(i);
307 
308  size_t vertexDescriptor = block.netlist().descriptor(port);
309  std::pair<out_edge_iterator, out_edge_iterator> edges =
310  boost::out_edges(vertexDescriptor, block.netlist());
311 
312  if (edges.first != edges.second) {
313  edge_descriptor edgeDescriptor = *edges.first;
314  vertex_descriptor dstVertex =
315  boost::target(edgeDescriptor, block.netlist());
316  NetlistPort* dstPort = block.netlist()[dstVertex];
317  if (&dstPort->parentBlock() != &block) {
318  stream << indentation(1) << "wire"
319  << portSignalType(port) << " "
320  << portSignalName(port) << ";" << endl;
321  }
322  } else if (!port.hasStaticValue()) {
323  // assume the port is connected to ground if is is
324  // unconnected in the netlist
325  if (port.realWidthAvailable()) {
326  groundWidth_ =
327  std::max(port.realWidth(), groundWidth_);
328  }
329  stream << indentation(1) << "wire"
330  << portSignalType(port) << " "
331  << portSignalName(port) << ";" << endl;
332  }
333  }
334  }
335 
336  // create a ground signal
337  if (groundWidth_ > 0) {
338  stream << indentation(1) << "wire[" << groundWidth_ - 1 << ":0]"
339  << GROUND_SIGNAL << ";" << endl;
340  }
341 }
342 
343 /**
344  * Writes the signal assignments of the given block to the given stream.
345  *
346  * @param block The netlist block.
347  * @param stream The stream.
348  */
349 void
351  const BaseNetlistBlock& block, std::ofstream& stream) const {
352  set<const BaseNetlistBlock*, NetlistBlockNameComparator> subBlocks;
353  for (size_t i = 0; i < block.subBlockCount(); i++) {
354  subBlocks.insert(&block.subBlock(i));
355  }
356 
357  typedef std::vector<edge_descriptor> EdgeTable;
358  EdgeTable handledEdges;
359 
360  for (size_t i = 0; i < block.subBlockCount(); i++) {
361  const BaseNetlistBlock& subBlock = block.subBlock(i);
362  for (size_t i = 0; i < subBlock.portCount(); i++) {
363  const NetlistPort& port = subBlock.port(i);
364  size_t vertexDescriptor = block.netlist().descriptor(port);
365  std::pair<out_edge_iterator, out_edge_iterator> edges =
366  boost::out_edges(vertexDescriptor, block.netlist());
367 
368  while (edges.first != edges.second) {
369  edge_descriptor edgeDescriptor = *edges.first;
370  edges.first++;
372  handledEdges, edgeDescriptor)) {
373  vertex_descriptor srcVertex =
374  boost::source(edgeDescriptor, block.netlist());
375  vertex_descriptor dstVertex =
376  boost::target(edgeDescriptor, block.netlist());
377  NetlistPort* srcPort = block.netlist()[srcVertex];
378  NetlistPort* dstPort = block.netlist()[dstVertex];
379 
380  if (&dstPort->parentBlock() == &block) {
381  continue;
382  }
383 
384  assert(srcPort == &port);
386  subBlocks, &srcPort->parentBlock()) &&
388  subBlocks, &dstPort->parentBlock())) {
389  handledEdges.push_back(edgeDescriptor);
390  // add the opposite edge too
391  std::pair<edge_descriptor, bool> opposite =
392  boost::edge(
393  dstVertex, srcVertex, block.netlist());
394  assert(opposite.second);
395  assert(opposite.first != edgeDescriptor);
396  handledEdges.push_back(opposite.first);
397 
398  PortConnectionProperty property =
399  block.netlist()[edgeDescriptor];
400  if (property.fullyConnected()) {
401  if (srcPort->direction() == OUT) {
402  stream << indentation(1) << "assign "
403  << portSignalName(*dstPort) << " = "
404  << portSignalName(*srcPort) << ";"
405  << endl;
406  } else {
407  stream << indentation(1) << "assign "
408  << portSignalName(*srcPort) << " = "
409  << portSignalName(*dstPort) << ";"
410  << endl;
411  }
412  } else {
413  string srcPortSignal;
414  if (srcPort->dataType() == BIT) {
415  srcPortSignal = portSignalName(*srcPort);
416  } else {
417  if (dstPort->dataType() == BIT) {
418  srcPortSignal =
419  portSignalName(*srcPort) + "[" +
421  property.port1FirstBit()) +
422  "]";
423  } else {
424  srcPortSignal =
425  portSignalName(*srcPort) + "[" +
427  property.port1FirstBit() +
428  property.width() - 1) +
429  ":" +
431  property.port1FirstBit()) +
432  "]";
433  }
434  }
435  string dstPortSignal;
436  if (dstPort->dataType() == BIT) {
437  dstPortSignal = portSignalName(*dstPort);
438  } else {
439  if (srcPort->dataType() == BIT) {
440  dstPortSignal =
441  portSignalName(*dstPort) + "[" +
443  property.port2FirstBit()) +
444  "]";
445  } else {
446  dstPortSignal =
447  portSignalName(*dstPort) + "[" +
449  property.port2FirstBit() +
450  property.width() - 1) +
451  ":" +
453  property.port2FirstBit()) +
454  "]";
455  }
456  }
457 
458  if (srcPort->direction() == OUT) {
459  stream << indentation(1) << "assign "
460  << dstPortSignal << " = "
461  << srcPortSignal << ";" << endl;
462  } else {
463  stream << indentation(1) << "assign "
464  << srcPortSignal << " = "
465  << dstPortSignal << ";" << endl;
466  }
467  }
468  }
469  }
470  }
471  }
472  }
473 
474  if (groundWidth_ > 0) {
475  stream << indentation(1) << "assign "
476  << GROUND_SIGNAL << " = {" << groundWidth_ <<"{1'b0}};"
477  << endl;
478  }
479 }
480 
481 /**
482  * Writes the port mappings of the given block to the given stream.
483  *
484  * @param block The netlist block.
485  * @param stream The stream to write.
486  */
487 void
489  const BaseNetlistBlock& block, std::ofstream& stream) const {
490  for (size_t i = 0; i < block.subBlockCount(); i++) {
491  const BaseNetlistBlock& component = block.subBlock(i);
492 
493  // virtual NetlistBlocks are omitted
494  if (component.isVirtual()) {
495  continue;
496  }
497 
498  stream << indentation(1) << component.moduleName()<< endl;
499 
500  // create generic map(parameters)
501  if (component.parameterCount() > 0) {
502  stream << indentation(1) << "#(" << endl;
503  for (size_t i = 0; i < component.parameterCount(); i++) {
504  Parameter param = component.parameter(i);
505  stream << indentation(2) << "." << param.name() << "(";
506 
507  if (param.type().lower() == PARAM_STRING) {
508  stream << genericMapStringValue(param.value());
509  } else {
510  stream << param.value();
511  }
512  if (i == component.parameterCount() - 1) {
513  stream << ")";
514  } else {
515  stream << "),";
516  }
517  stream << endl;
518  }
519  stream << indentation(1) << ")" << endl;
520  }
521  // create port map on unique(!) instance
522  stream << indentation(1) << component.instanceName()
523  << "_" << i << endl
524  << indentation(2) << "(" << endl;
525  for (size_t i = 0; i < component.portCount(); i++) {
526  const NetlistPort& port = component.port(i);
527  size_t vertexDescriptor = block.netlist().descriptor(port);
528  std::pair<out_edge_iterator, out_edge_iterator> edges =
529  boost::out_edges(vertexDescriptor, block.netlist());
530 
531  string srcConn = port.name();
532  string dstConn = "";
533  if (edges.first != edges.second) {
534  edge_descriptor edgeDescriptor = *edges.first;
535  vertex_descriptor dstVertex =
536  boost::target(edgeDescriptor, block.netlist());
537  NetlistPort* dstPort = block.netlist()[dstVertex];
538 
539  if (&dstPort->parentBlock() == &block) {
540  if (port.dataType() != dstPort->dataType()) {
541  if (port.dataType() == BIT) {
542  assert(dstPort->dataType() == BIT_VECTOR);
543  dstConn = dstPort->name() + "[0]";
544  } else {
545  assert(dstPort->dataType() == BIT);
546  srcConn += "[0]";
547  dstConn = dstPort->name();
548  }
549  } else {
550  dstConn = dstPort->name();
551  }
552  } else {
553  dstConn = portSignalName(port);
554  }
555  } else {
556  dstConn = portSignalName(port);
557  }
558  stream << indentation(3) << "." << srcConn << "(" << dstConn << ")";
559  if (i+1 < component.portCount()) {
560  stream << "," << endl;
561  }
562  }
563  stream << ");" << endl << endl;
564  }
565 }
566 
567 /**
568  * Returns the string that means the same direction as the given one in Verilog.
569  *
570  * @return The direction string.
571  */
572 std::string
574  switch (direction) {
575  case IN:
576  return "input";
577  case OUT:
578  return "output";
579  case BIDIR:
580  return "inout";
581  }
582  assert(false);
583  // dummy return
584  return "";
585 }
586 
587 /**
588  * Tells whether the given string is a non-negative integer number.
589  *
590  * @param formula The string.
591  * @return True if the given string is a non-negative integer number.
592  */
593 bool
594 VerilogNetlistWriter::isNumber(const std::string& formula) {
595  int length = formula.length();
596  for (int i = 0; i < length; i++) {
597  if (!isdigit(formula[i])) {
598  return false;
599  }
600  }
601  return true;
602 }
603 
604 
605 /**
606  * Returns a string which makes indetation of the given level.
607  *
608  * @param level The indentation level.
609  */
610 std::string
611 VerilogNetlistWriter::indentation(unsigned int level) const {
612  return StringTools::indent(level);
613 }
614 
615 /**
616  * Generates an indentation string with the given parameters.
617  *
618  * @param indentationLevel The level of indentation.
619  * @param indentation The string used as indentation (one level).
620  * @return The indentation of the given level.
621  */
622 std::string
624  unsigned int indentationLevel,
625  const std::string& indentation) {
626 
627  string generatedInd("");
628  for (unsigned int i = 0; i < indentationLevel; i++) {
629  generatedInd += indentation;
630  }
631  return generatedInd;
632 }
633 
634 
635 /**
636  * Returns the name of the signal mapped to the given port.
637  *
638  * @param port The port.
639  */
640 std::string
642  const BaseNetlistBlock* parentBlock = &port.parentBlock();
643  if (port.hasStaticValue()) {
644  return "{" + Conversion::toString(port.realWidth()) + "{" +
645  ((port.staticValue().is(StaticSignal::VCC)) ? "1'b1"
646  : "1'b0") +
647  "}}";
648  }
649  return parentBlock->instanceName() + "_" + port.name() +"_wire";
650 }
651 
652 
653 /**
654  * Returns the type of the signal mapped to the given port.
655  *
656  * @param port The port.
657  */
658 std::string
660  if (port.dataType() == BIT) {
661  return "";
662  } else {
663  if (port.realWidthAvailable()) {
664  int width = port.realWidth();
665  return "[" + Conversion::toString(width?width-1:0) + ":0]";
666  } else if (isNumber(port.widthFormula()) &&
667  (Conversion::toInt(port.widthFormula()) == 0)) {
668  return "[0:0]";
669  } else {
670  return "[" + port.widthFormula()+"-1: 0]";
671  }
672  }
673 }
674 
675 TCEString
677 
678  if (generic.startsWith("\"") && generic.endsWith("\"")) {
679  return generic;
680  }
681  std::vector<TCEString> unallowed;
682  unallowed.push_back(".");
683  unallowed.push_back("__");
684  for (unsigned int i = 0; i < unallowed.size(); i++) {
685  if (generic.find(unallowed.at(i)) != TCEString::npos) {
686  TCEString quoted;
687  quoted << "\"" << generic << "\"";
688  return quoted;
689  }
690  }
691  return generic;
692 }
693 }
ProGe::BaseNetlistBlock
Definition: BaseNetlistBlock.hh:59
Netlist.hh
ProGe::VerilogNetlistWriter::generateIndentation
static std::string generateIndentation(unsigned int level, const std::string &indentation)
Definition: VerilogNetlistWriter.cc:623
FileSystem.hh
ProGe::NetlistPort::parentBlock
const BaseNetlistBlock & parentBlock() const
Definition: NetlistPort.cc:400
TCEString::lower
TCEString lower() const
Definition: TCEString.cc:78
ProGe::VerilogNetlistWriter::directionString
static std::string directionString(Direction direction)
Definition: VerilogNetlistWriter.cc:573
TCEString::startsWith
bool startsWith(const std::string &str) const
PARAM_STRING
const std::string PARAM_STRING
Definition: VerilogNetlistWriter.cc:59
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
ProGe::VerilogNetlistWriter::writeSignalDeclarations
void writeSignalDeclarations(const BaseNetlistBlock &block, std::ofstream &stream)
Definition: VerilogNetlistWriter.cc:286
ProGe::BaseNetlistBlock::parameterCount
virtual size_t parameterCount() const
Definition: BaseNetlistBlock.cc:231
ProGe::Parameter::type
const TCEString & type() const
Definition: Parameter.cc:138
AssocTools::containsKey
static bool containsKey(const ContainerType &aContainer, const KeyType &aKey)
ProGe::NetlistPort::widthFormula
std::string widthFormula() const
Definition: NetlistPort.cc:316
ProGe::NetlistPort::direction
Direction direction() const
Definition: NetlistPort.cc:373
ProGe::BaseNetlistBlock::instanceName
const std::string & instanceName() const
Definition: BaseNetlistBlock.cc:135
ProGe::NetlistWriter
Definition: NetlistWriter.hh:47
ProGe::BIDIR
@ BIDIR
Bidirectional port.
Definition: ProGeTypes.hh:55
StringTools::indent
static std::string indent(int level)
Definition: StringTools.cc:319
ProGe::BaseNetlistBlock::package
virtual const std::string & package(size_t idx) const
Definition: BaseNetlistBlock.cc:699
ProGe::StaticSignal::VCC
@ VCC
All port signals set to high.
Definition: NetlistPort.hh:51
GROUND_SIGNAL
const std::string GROUND_SIGNAL
Definition: VerilogNetlistWriter.cc:58
ProGe::VerilogNetlistWriter::VerilogNetlistWriter
VerilogNetlistWriter(const BaseNetlistBlock &targetBlock)
Definition: VerilogNetlistWriter.cc:68
ProGe::VerilogNetlistWriter::writeBlock
void writeBlock(const BaseNetlistBlock &block, const std::string &dstDirectory)
Definition: VerilogNetlistWriter.cc:139
ProGe::VerilogNetlistWriter::writePortDeclaration
static void writePortDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
Definition: VerilogNetlistWriter.cc:241
ProGe::BaseNetlistBlock::netlist
virtual const Netlist & netlist() const
Definition: BaseNetlistBlock.cc:348
Conversion::toString
static std::string toString(const T &source)
ProGe::NetlistPort::staticValue
StaticSignal staticValue() const
Definition: NetlistPort.cc:429
FileSystem::fileIsCreatable
static bool fileIsCreatable(const std::string fileName)
Definition: FileSystem.cc:123
ProGe::VerilogNetlistWriter::writePortMappings
void writePortMappings(const BaseNetlistBlock &block, std::ofstream &stream) const
Definition: VerilogNetlistWriter.cc:488
StringTools.hh
assert
#define assert(condition)
Definition: Application.hh:86
ProGe::StaticSignal::is
bool is(State state)
Definition: NetlistPort.hh:57
ProGe::NetlistPort::realWidthAvailable
bool realWidthAvailable() const
Definition: NetlistPort.cc:334
ProGe::Netlist::parameterCount
size_t parameterCount() const
Definition: Netlist.cc:422
ProGe::VerilogNetlistWriter::write
virtual void write(const std::string &dstDirectory)
Definition: VerilogNetlistWriter.cc:86
InvalidData
Definition: Exception.hh:149
FileSystem::fileIsWritable
static bool fileIsWritable(const std::string fileName)
ProGe::VerilogNetlistWriter::writeNetlistParameterPackage
void writeNetlistParameterPackage(const std::string &dstDirectory) const
Definition: VerilogNetlistWriter.cc:104
TCEString::endsWith
bool endsWith(const std::string &str) const
ProGe::BaseNetlistBlock::parameter
virtual const Parameter & parameter(const std::string &name) const
Definition: BaseNetlistBlock.cc:198
Conversion.hh
ProGe::Parameter
Definition: Parameter.hh:62
NetlistPort.hh
ProGe::BaseNetlistBlock::portCount
virtual size_t portCount() const
Definition: BaseNetlistBlock.cc:248
ProGe::Parameter::name
const TCEString & name() const
Definition: Parameter.cc:133
ProGe::BaseNetlistBlock::packageCount
virtual size_t packageCount() const
Definition: BaseNetlistBlock.cc:694
__func__
#define __func__
Definition: Application.hh:67
NetlistBlock.hh
ProGe::Netlist::descriptor
size_t descriptor(const NetlistPort &port) const
Definition: Netlist.cc:325
ProGe::Parameter::value
const TCEString & value() const
Definition: Parameter.cc:143
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
ProGe::VerilogNetlistWriter::vertex_descriptor
boost::graph_traits< Netlist >::vertex_descriptor vertex_descriptor
Definition: VerilogNetlistWriter.hh:72
ProGe::VerilogNetlistWriter::edge_descriptor
boost::graph_traits< Netlist >::edge_descriptor edge_descriptor
Definition: VerilogNetlistWriter.hh:74
ProGe::NetlistPort::name
std::string name() const
Definition: NetlistPort.cc:283
ProGe::PortConnectionProperty
Definition: PortConnectionProperty.hh:51
ProGe::VerilogNetlistWriter::netlistParameterPkgName
std::string netlistParameterPkgName() const
Definition: VerilogNetlistWriter.cc:126
VerilogNetlistWriter.hh
FileSystem::DIRECTORY_SEPARATOR
static const std::string DIRECTORY_SEPARATOR
Definition: FileSystem.hh:189
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
ProGe::NetlistPort::dataType
DataType dataType() const
Definition: NetlistPort.cc:362
ProGe::VerilogNetlistWriter::groundWidth_
int groundWidth_
Width of the ground signal.
Definition: VerilogNetlistWriter.hh:117
ProGe::NetlistPort::realWidth
int realWidth() const
Definition: NetlistPort.cc:348
ProGe::VerilogNetlistWriter::portSignalType
static std::string portSignalType(const NetlistPort &port)
Definition: VerilogNetlistWriter.cc:659
ProGe::VerilogNetlistWriter::~VerilogNetlistWriter
virtual ~VerilogNetlistWriter()
Definition: VerilogNetlistWriter.cc:75
ProGe::VerilogNetlistWriter::isNumber
static bool isNumber(const std::string &formula)
Definition: VerilogNetlistWriter.cc:594
ProGe::Netlist::isEmpty
bool isEmpty() const
Definition: Netlist.cc:288
ProGe::NetlistWriter::targetNetlistBlock
const BaseNetlistBlock & targetNetlistBlock() const
Definition: NetlistWriter.cc:64
ProGe::VerilogNetlistWriter::portSignalName
static std::string portSignalName(const NetlistPort &port)
Definition: VerilogNetlistWriter.cc:641
ProGe
Definition: FUGen.hh:54
FileSystem::fileExists
static bool fileExists(const std::string fileName)
AssocTools.hh
ProGe::NetlistPort::hasStaticValue
bool hasStaticValue() const
Definition: NetlistPort.cc:423
TCEString
Definition: TCEString.hh:53
ProGe::Netlist::parameter
Parameter parameter(size_t index) const
Definition: Netlist.cc:434
ProGe::VerilogNetlistWriter::writeSignalAssignments
void writeSignalAssignments(const BaseNetlistBlock &block, std::ofstream &stream) const
Definition: VerilogNetlistWriter.cc:350
ProGe::NetlistPort
Definition: NetlistPort.hh:70
ProGe::BaseNetlistBlock::moduleName
const std::string & moduleName() const
Definition: BaseNetlistBlock.cc:140
ContainerTools::containsValue
static bool containsValue(const ContainerType &aContainer, const ElementType &aKey)
ProGe::BaseNetlistBlock::subBlock
virtual const BaseNetlistBlock & subBlock(size_t index) const
Definition: BaseNetlistBlock.cc:155
Conversion::toInt
static int toInt(const T &source)
IOException
Definition: Exception.hh:130
ProGe::Parameter::defaultValue
const TCEString & defaultValue() const
Definition: Parameter.cc:148
ProGe::BaseNetlistBlock::isVirtual
virtual bool isVirtual() const
Definition: BaseNetlistBlock.hh:112
ProGe::VerilogNetlistWriter::genericMapStringValue
TCEString genericMapStringValue(const TCEString &generic) const
Definition: VerilogNetlistWriter.cc:676
ProGe::VerilogNetlistWriter::indentation
std::string indentation(unsigned int level) const
Definition: VerilogNetlistWriter.cc:611
ProGe::Direction
Direction
Direction of the port.
Definition: ProGeTypes.hh:52
ProGe::VerilogNetlistWriter::writeGenericDeclaration
static void writeGenericDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
Definition: VerilogNetlistWriter.cc:203
Parameter.hh
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
ProGe::BaseNetlistBlock::subBlockCount
virtual size_t subBlockCount() const
Definition: BaseNetlistBlock.cc:150
ProGe::BaseNetlistBlock::port
virtual const NetlistPort & port(size_t index) const
Definition: BaseNetlistBlock.cc:253
ContainerTools.hh