OpenASIP  2.0
VerilogNetlistWriter.hh
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1 /*
2  Copyright (c) 2012-2015 Vinogradov Viacheslav.
3 
4  This file is going to be a part of TTA-Based Codesign Environment (TCE).
5 
6  Permission is hereby granted, free of charge, to any person obtaining a
7  copy of this software and associated documentation files (the "Software"),
8  to deal in the Software without restriction, including without limitation
9  the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  and/or sell copies of the Software, and to permit persons to whom the
11  Software is furnished to do so, subject to the following conditions:
12 
13  The above copyright notice and this permission notice shall be included in
14  all copies or substantial portions of the Software.
15 
16  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  DEALINGS IN THE SOFTWARE.
23  */
24 /**
25  * @file VerilogNetlistWriter.hh
26  *
27  * Declaration of VerilogNetlistWriter class based on VHDLnetlistWriter
28  *
29  * @author Vinogradov Viacheslav 2012
30  * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam.tut.fi)
31  * @note rating: red
32  */
33 
34 #ifndef TTA_VERILOG_NETLIST_WRITER_HH
35 #define TTA_VERILOG_NETLIST_WRITER_HH
36 
37 #include <map>
38 #include <string>
39 #include <boost/graph/graph_traits.hpp>
40 
41 #include "NetlistWriter.hh"
42 #include "Netlist.hh"
43 #include "ProGeTypes.hh"
44 
45 namespace ProGe {
46 
47 class BaseNetlistBlock;
48 
49 /**
50  * Writes Verilog files which implement the given netlist.
51  */
53 public:
54  VerilogNetlistWriter(const BaseNetlistBlock& targetBlock);
55  virtual ~VerilogNetlistWriter();
56 
57  virtual void write(const std::string& dstDirectory);
58 
59  static void writeGenericDeclaration(
60  const BaseNetlistBlock& block,
61  unsigned int indentationLevel,
62  const std::string& indentation,
63  std::ostream& stream);
64  static void writePortDeclaration(
65  const BaseNetlistBlock& block,
66  unsigned int indentationLevel,
67  const std::string& indentation,
68  std::ostream& stream);
69 
70 private:
71  typedef boost::graph_traits<Netlist>::vertex_descriptor
73  typedef boost::graph_traits<Netlist>::edge_descriptor
75  typedef boost::graph_traits<Netlist>::out_edge_iterator
77 
78  void writeNetlistParameterPackage(const std::string& dstDirectory) const;
79  std::string netlistParameterPkgName() const;
80  void writeBlock(
81  const BaseNetlistBlock& block, const std::string& dstDirectory);
83  const BaseNetlistBlock& block,
84  std::ofstream& stream);
86  const BaseNetlistBlock& block,
87  std::ofstream& stream) const;
88 
90  const BaseNetlistBlock& block,
91  std::ofstream& stream) const;
92  void writePortMappings(
93  const BaseNetlistBlock& block,
94  std::ofstream& stream) const;
95  std::string indentation(unsigned int level) const;
96 
97  /**
98  * Tries to determine whether the string generic needs quot marks for
99  * generic mapping
100  *
101  * If string literal contains '.', or "__" it cannot be a valid
102  * Verilog label (i.e. another generic), thus it needs quotation marks.
103  *
104  * @param generic String generic value
105  * @return Generic mapping string
106  */
107  TCEString genericMapStringValue(const TCEString& generic) const;
108 
109  static std::string directionString(Direction direction);
110  static std::string generateIndentation(
111  unsigned int level, const std::string& indentation);
112  static bool isNumber(const std::string& formula);
113  static std::string portSignalName(const NetlistPort& port);
114  static std::string portSignalType(const NetlistPort& port);
115 
116  /// Width of the ground signal.
118 
119 };
120 }
121 
122 #endif
ProGe::BaseNetlistBlock
Definition: BaseNetlistBlock.hh:59
ProGe::VerilogNetlistWriter::writeComponentDeclarations
void writeComponentDeclarations(const BaseNetlistBlock &block, std::ofstream &stream) const
Netlist.hh
ProGe::VerilogNetlistWriter::out_edge_iterator
boost::graph_traits< Netlist >::out_edge_iterator out_edge_iterator
Definition: VerilogNetlistWriter.hh:76
ProGe::VerilogNetlistWriter::generateIndentation
static std::string generateIndentation(unsigned int level, const std::string &indentation)
Definition: VerilogNetlistWriter.cc:623
ProGe::VerilogNetlistWriter::directionString
static std::string directionString(Direction direction)
Definition: VerilogNetlistWriter.cc:573
ProGe::VerilogNetlistWriter::writeSignalDeclarations
void writeSignalDeclarations(const BaseNetlistBlock &block, std::ofstream &stream)
Definition: VerilogNetlistWriter.cc:286
ProGe::NetlistWriter
Definition: NetlistWriter.hh:47
ProGe::VerilogNetlistWriter::VerilogNetlistWriter
VerilogNetlistWriter(const BaseNetlistBlock &targetBlock)
Definition: VerilogNetlistWriter.cc:68
ProGe::VerilogNetlistWriter::writeBlock
void writeBlock(const BaseNetlistBlock &block, const std::string &dstDirectory)
Definition: VerilogNetlistWriter.cc:139
ProGe::VerilogNetlistWriter::writePortDeclaration
static void writePortDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
Definition: VerilogNetlistWriter.cc:241
ProGe::VerilogNetlistWriter::writePortMappings
void writePortMappings(const BaseNetlistBlock &block, std::ofstream &stream) const
Definition: VerilogNetlistWriter.cc:488
NetlistWriter.hh
ProGe::VerilogNetlistWriter::write
virtual void write(const std::string &dstDirectory)
Definition: VerilogNetlistWriter.cc:86
ProGe::VerilogNetlistWriter::writeNetlistParameterPackage
void writeNetlistParameterPackage(const std::string &dstDirectory) const
Definition: VerilogNetlistWriter.cc:104
ProGe::VerilogNetlistWriter::vertex_descriptor
boost::graph_traits< Netlist >::vertex_descriptor vertex_descriptor
Definition: VerilogNetlistWriter.hh:72
ProGe::VerilogNetlistWriter::edge_descriptor
boost::graph_traits< Netlist >::edge_descriptor edge_descriptor
Definition: VerilogNetlistWriter.hh:74
ProGeTypes.hh
ProGe::VerilogNetlistWriter::netlistParameterPkgName
std::string netlistParameterPkgName() const
Definition: VerilogNetlistWriter.cc:126
ProGe::VerilogNetlistWriter::groundWidth_
int groundWidth_
Width of the ground signal.
Definition: VerilogNetlistWriter.hh:117
ProGe::VerilogNetlistWriter::portSignalType
static std::string portSignalType(const NetlistPort &port)
Definition: VerilogNetlistWriter.cc:659
ProGe::VerilogNetlistWriter::~VerilogNetlistWriter
virtual ~VerilogNetlistWriter()
Definition: VerilogNetlistWriter.cc:75
ProGe::VerilogNetlistWriter::isNumber
static bool isNumber(const std::string &formula)
Definition: VerilogNetlistWriter.cc:594
ProGe::VerilogNetlistWriter::portSignalName
static std::string portSignalName(const NetlistPort &port)
Definition: VerilogNetlistWriter.cc:641
ProGe
Definition: FUGen.hh:54
TCEString
Definition: TCEString.hh:53
ProGe::VerilogNetlistWriter::writeSignalAssignments
void writeSignalAssignments(const BaseNetlistBlock &block, std::ofstream &stream) const
Definition: VerilogNetlistWriter.cc:350
ProGe::NetlistPort
Definition: NetlistPort.hh:70
ProGe::VerilogNetlistWriter
Definition: VerilogNetlistWriter.hh:52
ProGe::VerilogNetlistWriter::genericMapStringValue
TCEString genericMapStringValue(const TCEString &generic) const
Definition: VerilogNetlistWriter.cc:676
ProGe::VerilogNetlistWriter::indentation
std::string indentation(unsigned int level) const
Definition: VerilogNetlistWriter.cc:611
ProGe::Direction
Direction
Direction of the port.
Definition: ProGeTypes.hh:52
ProGe::VerilogNetlistWriter::writeGenericDeclaration
static void writeGenericDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
Definition: VerilogNetlistWriter.cc:203