OpenASIP  2.0
Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | Static Private Attributes | List of all members
AlmaIFIntegrator Class Reference

#include <AlmaIFIntegrator.hh>

Inheritance diagram for AlmaIFIntegrator:
Inheritance graph
Collaboration diagram for AlmaIFIntegrator:
Collaboration graph

Public Member Functions

 AlmaIFIntegrator ()
 
 AlmaIFIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString entityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType, bool syncReset)
 
virtual ~AlmaIFIntegrator ()
 
virtual void integrateProcessor (const ProGe::NetlistBlock *progeBlock)
 
virtual bool integrateCore (const ProGe::NetlistBlock &cores, int coreId)
 
virtual void printInfo (std::ostream &stream) const
 
virtual TCEString deviceFamily () const
 
virtual void setDeviceFamily (TCEString devFamily)
 
virtual TCEString devicePackage () const
 
virtual TCEString deviceSpeedClass () const
 
virtual int targetClockFrequency () const
 
virtual TCEString pinTag () const
 
virtual bool chopTaggedSignals () const
 
virtual ProjectFileGenerator * projectFileGenerator () const
 
- Public Member Functions inherited from PlatformIntegrator
 PlatformIntegrator ()
 
 PlatformIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)
 
virtual ~PlatformIntegrator ()
 
void setDeviceName (TCEString devName)
 
TCEString deviceName () const
 
const ProGe::NetlistBlock & progeBlock () const
 
const ProGe::NetlistBlock & toplevelBlock () const
 
void setSharedOutputDir (const TCEString &sharedDir)
 
TCEString outputPath () const
 
TCEString outputFilePath (TCEString fileName, bool absolute=false) const
 
TCEString coreEntityName () const
 
const TTAMachine::Machine * machine () const
 
const IDF::MachineImplementation * idf () const
 
const MemInfo & imemInfo () const
 
const MemInfo & dmemInfo (TTAMachine::AddressSpace *as) const
 
const MemInfo & dmemInfo (int index) const
 
int dmemCount () const
 
ProGe::NetlistPort * clockPort () const
 
ProGe::NetlistPort * resetPort () const
 

Protected Member Functions

virtual MemoryGenerator & imemInstance (MemInfo imem, int coreId)
 
virtual MemoryGenerator & dmemInstance (MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
 
- Protected Member Functions inherited from PlatformIntegrator
ProGe::NetlistBlock * integratorBlock ()
 
virtual void initPlatformNetlist (const ProGe::NetlistBlock *progeBlock)
 
virtual void connectToplevelPort (const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")
 
virtual bool hasPinTag (const TCEString &signal) const
 
void copyProgeBlockToNetlist (const ProGe::NetlistBlock *progeBlock)
 
virtual bool createMemories (int coreId)
 
virtual bool generateMemory (MemoryGenerator &memGen, std::vector< TCEString > &generatedFiles, int memIndex, int coreId)
 
virtual void writeNewToplevel ()
 
void addProGeFiles () const
 
TCEString programName () const
 
TCEString progeFilePath (TCEString fileName, bool absolute=false) const
 
TCEString chopSignalToTag (const TCEString &original, const TCEString &tag) const
 
void progeOutputHdlFiles (std::vector< TCEString > &files) const
 
std::ostream & warningStream () const
 
std::ostream & errorStream () const
 
TCEString platformEntityName () const
 
void parseDataMemories ()
 
void clearDataMemories ()
 
MemInfo readLsuParameters (const TTAMachine::FunctionUnit &lsu)
 

Private Member Functions

void addMemoryPorts (const TCEString as_name, int data_width, int addr_width, const bool isShared, const bool overrideAsWidth)
 
void addMemoryPorts (const TCEString as_name, int mem_count, int data_width, int addr_width, int strb_width, const bool overrideAsWidth)
 
void initAlmaifBlock ()
 
void addAlmaifFiles ()
 
void copyPlatformFile (const TCEString inputPath, std::vector< TCEString > &fileList, bool isScript=false) const
 
TCEString axiAddressWidth () const
 
void findMemories ()
 
void exportUnconnectedPorts (int coreId)
 
void connectCoreMemories (MemInfo mem, TCEString mem_name, TCEString mem_block_name, bool seconds)
 
void addPortToGroup (ProGe::NetlistPortGroup *port_group, const ProGe::Direction dir, const TCEString name, const TCEString width)
 
void addPortToAlmaIFBlock (const TCEString name, const TCEString width, const ProGe::Direction dir, const TCEString core_name="")
 
void addPortToAlmaIFBlock (const TCEString name, const int width, const ProGe::Direction dir, const TCEString core_name="")
 
ProGe::NetlistPortGroup * axiSlavePortGroup ()
 
ProGe::NetlistPortGroup * axiMasterPortGroup ()
 

Private Attributes

MemoryGenerator * imemGen_
 
std::map< TCEString, MemoryGenerator * > dmemGen_
 
std::map< TCEString, ProGe::NetlistPort * > almaif_ttacore_ports
 
ProGe::NetlistBlock * almaifBlock_
 
TCEString deviceFamily_
 
TCEString deviceName_
 
DefaultProjectFileGenerator * fileGen_
 
MemInfo dmemInfo_
 
MemInfo pmemInfo_
 
bool secondDmem_
 
bool secondPmem_
 
bool dmemHandled_
 
bool pmemHandled_
 
std::string secondDmemName_
 
int secondDmemDataw_ = 0
 
int secondDmemAddrw_ = 0
 
std::string secondPmemName_
 
int secondPmemDataw_
 
int secondPmemAddrw_
 
HDLTemplateInstantiator accelInstantiator_
 
bool hasMinimalDebugger_
 
bool hasSeparateLocalMemory_ = true
 
bool syncReset_
 
bool broadcast_pmem_
 
bool dmem_dram_ = false
 
bool imem_dp_ = false
 

Static Private Attributes

static const TCEString DMEM_NAME = "data"
 
static const TCEString PMEM_NAME = "param"
 
static const TCEString AXI_AS_NAME = "axi_as"
 
static const TCEString ALMAIF_MODULE = "tta_accel"
 
static const TCEString DEFAULT_DEVICE = "xc7z020clg400-1"
 
static const int DEFAULT_RESERVED_PRIVATE_MEM_SIZE = 2048
 
static const int DEFAULT_LOCAL_MEMORY_WIDTH = 12
 

Additional Inherited Members

- Static Protected Attributes inherited from PlatformIntegrator
static const TCEString TTA_CORE_CLK = "clk"
 
static const TCEString TTA_CORE_RSTX = "rstx"
 

Detailed Description

Definition at line 40 of file AlmaIFIntegrator.hh.

Constructor & Destructor Documentation

◆ AlmaIFIntegrator() [1/2]

AlmaIFIntegrator::AlmaIFIntegrator ( )

Definition at line 61 of file AlmaIFIntegrator.cc.

61  : PlatformIntegrator() {
62 }

◆ AlmaIFIntegrator() [2/2]

AlmaIFIntegrator::AlmaIFIntegrator ( const TTAMachine::Machine *  machine,
const IDF::MachineImplementation *  idf,
ProGe::HDL  hdl,
TCEString  progeOutputDir,
TCEString  entityName,
TCEString  outputDir,
TCEString  programName,
int  targetClockFreq,
std::ostream &  warningStream,
std::ostream &  errorStream,
const MemInfo &  imem,
MemType  dmemType,
bool  syncReset 
)

Definition at line 64 of file AlmaIFIntegrator.cc.

70  : PlatformIntegrator(
71  machine, idf, hdl, progeOutputDir, coreEntityName, outputDir,
72  programName, targetClockFreq, warningStream, errorStream, imem,
73  dmemType),
74  imemGen_(NULL),
75  dmemGen_(),
76  almaifBlock_(NULL),
77  deviceFamily_(""),
78  fileGen_(new DefaultProjectFileGenerator(coreEntityName, this)),
79  secondDmem_(false),
80  secondPmem_(false),
81  dmemHandled_(false),
82  pmemHandled_(false),
83  syncReset_(syncReset),
84  broadcast_pmem_(false) {
85  if (idf->icDecoderParameterValue("debugger") == "external") {
86  hasMinimalDebugger_ = false;
87  } else if (idf->icDecoderParameterValue("debugger") == "minimal") {
88  hasMinimalDebugger_ = true;
89  } else {
90  TCEString msg =
91  "AlmaIF interface requires connections to an external debugger.";
92  throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
93  }
94 }

References hasMinimalDebugger_, IDF::MachineImplementation::icDecoderParameterValue(), and PlatformIntegrator::idf().

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◆ ~AlmaIFIntegrator()

AlmaIFIntegrator::~AlmaIFIntegrator ( )
virtual

Definition at line 96 of file AlmaIFIntegrator.cc.

96  {
97 
98  if (imemGen_ != NULL) {
99  delete imemGen_;
100  }
101  if (!dmemGen_.empty()) {
102  std::map<TCEString, MemoryGenerator*>::iterator iter =
103  dmemGen_.begin();
104  while (iter != dmemGen_.end()) {
105  delete iter->second;
106  iter++;
107  }
108  }
109 }

References dmemGen_, and imemGen_.

Member Function Documentation

◆ addAlmaifFiles()

void AlmaIFIntegrator::addAlmaifFiles ( )
private

Definition at line 817 of file AlmaIFIntegrator.cc.

817  {
818  const std::string DS = FileSystem::DIRECTORY_SEPARATOR;
819  std::vector<TCEString> almaifFiles;
820 
821  TCEString basePath = Environment::dataDirPath("ProGe");
822  TCEString platformPath = basePath + DS + "platform" + DS;
823  TCEString dbPath = basePath + DS + "debugger" + DS;
824 
825  TCEString outputPath = outputFilePath("tta-accel.vhdl", true);
826  if (pmemInfo_.asAddrw == 32) {
827  Path snippet(platformPath + "axi_master_port_declaration.snippet");
828  accelInstantiator_.replacePlaceholderFromFile(
829  "m-axi-port-declarations", snippet);
830  } else {
831  Path snippet(platformPath + "axi_master_signal_declaration.snippet");
832  accelInstantiator_.replacePlaceholderFromFile(
833  "m-axi-signal-declarations", snippet);
834  }
835 
836  accelInstantiator_.instantiateTemplateFile(
837  platformPath + "tta-accel.vhdl.tmpl", outputPath);
838  almaifFiles.push_back(outputPath);
839 
840  copyPlatformFile(platformPath + "tta-axislave.vhdl", almaifFiles);
841  copyPlatformFile(platformPath + "almaif_decoder.vhdl", almaifFiles);
842  copyPlatformFile(platformPath + "almaif_axi_arbiter.vhdl", almaifFiles);
843  copyPlatformFile(platformPath + "almaif_mc_arbiter.vhdl", almaifFiles);
844  copyPlatformFile(platformPath + "almaif_axi_expander.vhdl", almaifFiles);
845  copyPlatformFile(platformPath + "membus_splitter.vhdl", almaifFiles);
846  copyPlatformFile(platformPath + "almaif_membus_delay.vhdl", almaifFiles);
847  copyPlatformFile(dbPath + "registers-pkg.vhdl", almaifFiles);
848 
849  if (hasMinimalDebugger_) {
850  copyPlatformFile(dbPath + "minidebugger.vhdl", almaifFiles);
851  } else {
852  copyPlatformFile(dbPath + "dbregbank.vhdl", almaifFiles);
853  copyPlatformFile(dbPath + "dbsm-entity.vhdl", almaifFiles);
854  copyPlatformFile(dbPath + "dbsm-rtl.vhdl", almaifFiles);
855  copyPlatformFile(dbPath + "debugger.vhdl", almaifFiles);
856  }
857 
858  // Copy synthesis scripts
859  TCEString scriptPath = basePath + DS + "synthesis" + DS;
860  accelInstantiator_.replacePlaceholder("part_name", deviceName());
861  accelInstantiator_.replacePlaceholder(
862  "toplevel_entity", coreEntityName() + "_toplevel");
863  copyPlatformFile(scriptPath + "find_fmax.py", almaifFiles, true);
864  outputPath = progeFilePath("timing.tcl", true);
865  accelInstantiator_.instantiateTemplateFile(
866  scriptPath + "timing.tcl.tmpl", outputPath);
867  outputPath = progeFilePath("utilization.tcl", true);
868  accelInstantiator_.instantiateTemplateFile(
869  scriptPath + "utilization.tcl.tmpl", outputPath);
870 
871  for (unsigned int i = 0; i < almaifFiles.size(); i++) {
872  projectFileGenerator()->addHdlFile(almaifFiles.at(i));
873  }
874 }

References accelInstantiator_, ProjectFileGenerator::addHdlFile(), MemInfo::asAddrw, copyPlatformFile(), PlatformIntegrator::coreEntityName(), Environment::dataDirPath(), PlatformIntegrator::deviceName(), FileSystem::DIRECTORY_SEPARATOR, DS, hasMinimalDebugger_, HDLTemplateInstantiator::instantiateTemplateFile(), PlatformIntegrator::outputFilePath(), PlatformIntegrator::outputPath(), pmemInfo_, PlatformIntegrator::progeFilePath(), projectFileGenerator(), HDLTemplateInstantiator::replacePlaceholder(), and HDLTemplateInstantiator::replacePlaceholderFromFile().

Referenced by integrateProcessor().

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◆ addMemoryPorts() [1/2]

void AlmaIFIntegrator::addMemoryPorts ( const TCEString  as_name,
int  data_width,
int  addr_width,
const bool  isShared,
const bool  overrideAsWidth 
)
private

Definition at line 778 of file AlmaIFIntegrator.cc.

780  {
781  int mem_count = 1;
782 
783  data_width = data_width * mem_count;
784  addr_width = addr_width * mem_count;
785  // In case the data_width has been already multiplied by the mem_count,
786  // we have to undo the multiplication, so the rounding is done properly
787  // for the single memory version and only then multiplied by the
788  // mem_count.
789  int strb_width = (data_width / mem_count + 7) / 8 * mem_count;
790 
791  addMemoryPorts(
792  prefix, mem_count, data_width, addr_width, strb_width,
793  overrideAsWidth);
794 }

Referenced by connectCoreMemories(), and initAlmaifBlock().

◆ addMemoryPorts() [2/2]

void AlmaIFIntegrator::addMemoryPorts ( const TCEString  as_name,
int  mem_count,
int  data_width,
int  addr_width,
int  strb_width,
const bool  overrideAsWidth 
)
private

Definition at line 797 of file AlmaIFIntegrator.cc.

799  {
800  addPortToAlmaIFBlock(prefix + "_avalid_out", mem_count, ProGe::OUT);
801  addPortToAlmaIFBlock(prefix + "_aready_in", mem_count, ProGe::IN);
802  if (overrideAsWidth) {
803  addPortToAlmaIFBlock(
804  prefix + "_aaddr_out", "local_mem_addrw_g", ProGe::OUT);
805  } else {
806  addPortToAlmaIFBlock(prefix + "_aaddr_out", addr_width, ProGe::OUT);
807  }
808  addPortToAlmaIFBlock(prefix + "_awren_out", mem_count, ProGe::OUT);
809  addPortToAlmaIFBlock(prefix + "_astrb_out", strb_width, ProGe::OUT);
810  addPortToAlmaIFBlock(prefix + "_adata_out", data_width, ProGe::OUT);
811  addPortToAlmaIFBlock(prefix + "_rvalid_in", mem_count, ProGe::IN);
812  addPortToAlmaIFBlock(prefix + "_rready_out", mem_count, ProGe::OUT);
813  addPortToAlmaIFBlock(prefix + "_rdata_in", data_width, ProGe::IN);
814 }

References addPortToAlmaIFBlock(), ProGe::IN, and ProGe::OUT.

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◆ addPortToAlmaIFBlock() [1/2]

void AlmaIFIntegrator::addPortToAlmaIFBlock ( const TCEString  name,
const int  width,
const ProGe::Direction  dir,
const TCEString  core_name = "" 
)
private

Definition at line 688 of file AlmaIFIntegrator.cc.

690  {
691  NetlistPort* port = new NetlistPort(
692  name, Conversion::toString(width), width, ProGe::BIT_VECTOR, dir,
693  *almaifBlock_);
694  if (core_name != "") almaif_ttacore_ports[core_name] = port;
695 }

References almaif_ttacore_ports, almaifBlock_, ProGe::BIT_VECTOR, and Conversion::toString().

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◆ addPortToAlmaIFBlock() [2/2]

void AlmaIFIntegrator::addPortToAlmaIFBlock ( const TCEString  name,
const TCEString  width,
const ProGe::Direction  dir,
const TCEString  core_name = "" 
)
private

Definition at line 679 of file AlmaIFIntegrator.cc.

681  {
682  NetlistPort* port =
683  new NetlistPort(name, width, ProGe::BIT_VECTOR, dir, *almaifBlock_);
684  if (core_name != "") almaif_ttacore_ports[core_name] = port;
685 }

References almaif_ttacore_ports, almaifBlock_, and ProGe::BIT_VECTOR.

Referenced by addMemoryPorts(), connectCoreMemories(), and initAlmaifBlock().

◆ addPortToGroup()

void AlmaIFIntegrator::addPortToGroup ( ProGe::NetlistPortGroup *  port_group,
const ProGe::Direction  dir,
const TCEString  name,
const TCEString  width 
)
private

Definition at line 698 of file AlmaIFIntegrator.cc.

700  {
701  ProGe::DataType type = ProGe::BIT_VECTOR;
702  if (width == "1") {
703  type = ProGe::BIT;
704  }
705  NetlistPort* port = new NetlistPort(name, width, type, dir);
706  port_group->addPort(*port);
707 }

References ProGe::NetlistPortGroup::addPort(), ProGe::BIT, and ProGe::BIT_VECTOR.

Referenced by axiMasterPortGroup(), and axiSlavePortGroup().

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◆ axiAddressWidth()

TCEString AlmaIFIntegrator::axiAddressWidth ( ) const
private

Returns the AXI bus facing address width: 2 bits for address space select

  • maximum of the four address space widths (byte-addressed):
  • CTRL block (fixed 1024 bytes per core)
  • Instruction memory
  • Data and parameter memories

Definition at line 237 of file AlmaIFIntegrator.cc.

237  {
238  // IMEM address width
239  int imemAddressWidth = 0;
240  if (imemInfo().type != VHDL_ARRAY) {
241  imemAddressWidth =
242  MathTools::requiredBits0Bit0(
243  (imemInfo().widthInMaus * imemInfo().mauWidth + 7) / 8 - 1) +
244  imemInfo().portAddrw;
245  }
246  // Debugger address space:
247  int debugAddressWidth = 8;
248  int dmemAddressWidth =
249  dmemInfo_.portAddrw +
250  MathTools::requiredBits0Bit0(
251  std::max(0, dmemInfo_.mauWidth * dmemInfo_.widthInMaus / 8 - 1));
252 
253  // Skip param if its width is set by a generic: if there is a larger
254  // memory (imem/dmem), the value will still be correct
255  int pmemAddressWidth = 0;
256  if (pmemInfo_.asAddrw != 32) {
257  pmemAddressWidth =
258  pmemInfo_.portAddrw +
259  MathTools::requiredBits0Bit0(std::max(
260  0, pmemInfo_.mauWidth * pmemInfo_.widthInMaus / 8 - 1));
261  } else {
262  pmemAddressWidth = DEFAULT_LOCAL_MEMORY_WIDTH;
263  }
264  int axiAddressWidth = std::max(
265  std::max(imemAddressWidth, debugAddressWidth),
266  std::max(dmemAddressWidth, pmemAddressWidth));
267 
268  return Conversion::toString(axiAddressWidth + 2);
269 }

References MemInfo::asAddrw, DEFAULT_LOCAL_MEMORY_WIDTH, dmemInfo_, PlatformIntegrator::imemInfo(), MemInfo::mauWidth, pmemInfo_, MemInfo::portAddrw, MathTools::requiredBits0Bit0(), Conversion::toString(), VHDL_ARRAY, and MemInfo::widthInMaus.

Referenced by initAlmaifBlock().

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◆ axiMasterPortGroup()

NetlistPortGroup * AlmaIFIntegrator::axiMasterPortGroup ( )
private

Builds a representation of the AXI4-Lite master interface as a port group.

Definition at line 753 of file AlmaIFIntegrator.cc.

753  {
754  NetlistPortGroup* axiBus = new NetlistPortGroup(ProGe::SignalGroup());
755 
756  addPortToGroup(axiBus, ProGe::OUT, "m_axi_awaddr", "32");
757  addPortToGroup(axiBus, ProGe::OUT, "m_axi_awvalid", "1");
758  addPortToGroup(axiBus, ProGe::IN, "m_axi_awready", "1");
759  addPortToGroup(axiBus, ProGe::OUT, "m_axi_awprot", "3");
760  addPortToGroup(axiBus, ProGe::OUT, "m_axi_wvalid", "1");
761  addPortToGroup(axiBus, ProGe::IN, "m_axi_wready", "1");
762  addPortToGroup(axiBus, ProGe::OUT, "m_axi_wdata", "32");
763  addPortToGroup(axiBus, ProGe::OUT, "m_axi_wstrb", "4");
764  addPortToGroup(axiBus, ProGe::IN, "m_axi_bvalid", "1");
765  addPortToGroup(axiBus, ProGe::OUT, "m_axi_bready", "1");
766  addPortToGroup(axiBus, ProGe::OUT, "m_axi_arvalid", "1");
767  addPortToGroup(axiBus, ProGe::IN, "m_axi_arready", "1");
768  addPortToGroup(axiBus, ProGe::OUT, "m_axi_araddr", "32");
769  addPortToGroup(axiBus, ProGe::OUT, "m_axi_arprot", "3");
770  addPortToGroup(axiBus, ProGe::IN, "m_axi_rdata", "32");
771  addPortToGroup(axiBus, ProGe::IN, "m_axi_rvalid", "1");
772  addPortToGroup(axiBus, ProGe::OUT, "m_axi_rready", "1");
773 
774  return axiBus;
775 }

References addPortToGroup(), ProGe::IN, and ProGe::OUT.

Referenced by initAlmaifBlock().

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◆ axiSlavePortGroup()

NetlistPortGroup * AlmaIFIntegrator::axiSlavePortGroup ( )
private

Builds a representation of the AXI4 bus slave interface as a port group. Hardcoded signal widths for data (32b) and IDs (12b)

Definition at line 714 of file AlmaIFIntegrator.cc.

714  {
715  NetlistPortGroup* axiBus = new NetlistPortGroup(ProGe::SignalGroup());
716 
717  addPortToGroup(axiBus, ProGe::IN, "s_axi_awid", "axi_id_width_g");
718  addPortToGroup(axiBus, ProGe::IN, "s_axi_awaddr", "axi_addr_width_g");
719  addPortToGroup(axiBus, ProGe::IN, "s_axi_awlen", "8");
720  addPortToGroup(axiBus, ProGe::IN, "s_axi_awsize", "3");
721  addPortToGroup(axiBus, ProGe::IN, "s_axi_awburst", "2");
722  addPortToGroup(axiBus, ProGe::IN, "s_axi_awvalid", "1");
723  addPortToGroup(axiBus, ProGe::OUT, "s_axi_awready", "1");
724  addPortToGroup(axiBus, ProGe::IN, "s_axi_wdata", "32");
725  addPortToGroup(axiBus, ProGe::IN, "s_axi_wstrb", "4");
726  addPortToGroup(axiBus, ProGe::IN, "s_axi_wvalid", "1");
727  addPortToGroup(axiBus, ProGe::OUT, "s_axi_wready", "1");
728  addPortToGroup(axiBus, ProGe::OUT, "s_axi_bid", "axi_id_width_g");
729  addPortToGroup(axiBus, ProGe::OUT, "s_axi_bresp", "2");
730  addPortToGroup(axiBus, ProGe::OUT, "s_axi_bvalid", "1");
731  addPortToGroup(axiBus, ProGe::IN, "s_axi_bready", "1");
732  addPortToGroup(axiBus, ProGe::IN, "s_axi_arid", "axi_id_width_g");
733  addPortToGroup(axiBus, ProGe::IN, "s_axi_araddr", "axi_addr_width_g");
734  addPortToGroup(axiBus, ProGe::IN, "s_axi_arlen", "8");
735  addPortToGroup(axiBus, ProGe::IN, "s_axi_arsize", "3");
736  addPortToGroup(axiBus, ProGe::IN, "s_axi_arburst", "2");
737  addPortToGroup(axiBus, ProGe::IN, "s_axi_arvalid", "1");
738  addPortToGroup(axiBus, ProGe::OUT, "s_axi_arready", "1");
739  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rid", "axi_id_width_g");
740  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rdata", "32");
741  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rresp", "2");
742  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rlast", "1");
743  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rvalid", "1");
744  addPortToGroup(axiBus, ProGe::IN, "s_axi_rready", "1");
745 
746  return axiBus;
747 }

References addPortToGroup(), ProGe::IN, and ProGe::OUT.

Referenced by initAlmaifBlock().

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◆ chopTaggedSignals()

bool AlmaIFIntegrator::chopTaggedSignals ( ) const
virtual

Implements PlatformIntegrator.

Definition at line 1114 of file AlmaIFIntegrator.cc.

1114  {
1115  return true;
1116 }

◆ connectCoreMemories()

void AlmaIFIntegrator::connectCoreMemories ( MemInfo  mem,
TCEString  mem_name,
TCEString  mem_block_name,
bool  seconds 
)
private

Definition at line 553 of file AlmaIFIntegrator.cc.

554  {
555  almaifBlock_->setParameter(
556  mem_name + "_data_width_g", "integer",
557  Conversion::toString(mem.mauWidth * mem.widthInMaus));
558  almaifBlock_->setParameter(
559  mem_name + "_addr_width_g", "integer",
560  Conversion::toString(mem.portAddrw));
561 
562  TCEString platformPath = Environment::dataDirPath("ProGe");
563  platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
564  << FileSystem::DIRECTORY_SEPARATOR;
565 
566  // If given memory wasn't found by findMemories(), we need dummy signals
567  // as a stand-in for the missing ports
568  if (mem.portAddrw == 0 || mem.type == DRAM) {
569  Path snippet(platformPath + mem_name + "_signal_declaration.snippet");
570  accelInstantiator_.replacePlaceholderFromFile(
571  mem_name + "-signal-declarations", snippet);
572  return;
573  }
574 
575  // Otherwise, instantiate the ports
576  if (mem_name == "pmem" && broadcast_pmem_) {
577  Path snippet(platformPath + "pmem_port_declaration_wide.snippet");
578  accelInstantiator_.replacePlaceholderFromFile(
579  mem_name + "-port-declarations", snippet);
580  } else {
581  Path snippet(platformPath + mem_name + "_port_declaration.snippet");
582  accelInstantiator_.replacePlaceholderFromFile(
583  mem_name + "-port-declarations", snippet);
584  }
585 
586  TCEString lsu_prefix = "fu_" + mem.lsuName;
587 
588  int coreCount = 1;
589  addPortToAlmaIFBlock(
590  "core_" + mem_name + "_avalid_in", coreCount, ProGe::IN,
591  lsu_prefix + "_avalid_out");
592  addPortToAlmaIFBlock(
593  "core_" + mem_name + "_aready_out", coreCount, ProGe::OUT,
594  lsu_prefix + "_aready_in");
595  addPortToAlmaIFBlock(
596  "core_" + mem_name + "_aaddr_in", coreCount * mem.portAddrw,
597  ProGe::IN, lsu_prefix + "_aaddr_out");
598  addPortToAlmaIFBlock(
599  "core_" + mem_name + "_awren_in", coreCount, ProGe::IN,
600  lsu_prefix + "_awren_out");
601  addPortToAlmaIFBlock(
602  "core_" + mem_name + "_astrb_in",
603  (mem.mauWidth * mem.widthInMaus + 7) / 8 * coreCount, ProGe::IN,
604  lsu_prefix + "_astrb_out");
605 
606  addPortToAlmaIFBlock(
607  "core_" + mem_name + "_adata_in",
608  coreCount * mem.mauWidth * mem.widthInMaus, ProGe::IN,
609  lsu_prefix + "_adata_out");
610  addPortToAlmaIFBlock(
611  "core_" + mem_name + "_rvalid_out", coreCount, ProGe::OUT,
612  lsu_prefix + "_rvalid_in");
613  addPortToAlmaIFBlock(
614  "core_" + mem_name + "_rready_in", coreCount, ProGe::IN,
615  lsu_prefix + "_rready_out");
616  addPortToAlmaIFBlock(
617  "core_" + mem_name + "_rdata_out",
618  coreCount * mem.mauWidth * mem.widthInMaus, ProGe::OUT,
619  lsu_prefix + "_rdata_in");
620 
621  if (seconds) {
622  int addrWidth, dataWidth;
623  if (mem.asName == DMEM_NAME) {
624  addrWidth = secondDmemAddrw_;
625  dataWidth = secondDmemDataw_;
626  lsu_prefix = "fu_" + secondDmemName_;
627  } else {
628  addrWidth = secondPmemAddrw_;
629  dataWidth = secondPmemDataw_;
630  lsu_prefix = "fu_" + secondPmemName_;
631  }
632  addPortToAlmaIFBlock(
633  "core_" + mem_name + "_2nd_avalid_in", coreCount, ProGe::IN,
634  lsu_prefix + "_avalid_out");
635  addPortToAlmaIFBlock(
636  "core_" + mem_name + "_2nd_aready_out", coreCount, ProGe::OUT,
637  lsu_prefix + "_aready_in");
638  addPortToAlmaIFBlock(
639  "core_" + mem_name + "_2nd_aaddr_in", coreCount * addrWidth,
640  ProGe::IN, lsu_prefix + "_aaddr_out");
641  addPortToAlmaIFBlock(
642  "core_" + mem_name + "_2nd_awren_in", coreCount, ProGe::IN,
643  lsu_prefix + "_awren_out");
644  addPortToAlmaIFBlock(
645  "core_" + mem_name + "_2nd_astrb_in", coreCount * dataWidth / 8,
646  ProGe::IN, lsu_prefix + "_astrb_out");
647 
648  addPortToAlmaIFBlock(
649  "core_" + mem_name + "_2nd_adata_in", coreCount * dataWidth,
650  ProGe::IN, lsu_prefix + "_adata_out");
651  addPortToAlmaIFBlock(
652  "core_" + mem_name + "_2nd_rvalid_out", coreCount, ProGe::OUT,
653  lsu_prefix + "_rvalid_in");
654  addPortToAlmaIFBlock(
655  "core_" + mem_name + "_2nd_rready_in", coreCount, ProGe::IN,
656  lsu_prefix + "_rready_out");
657  addPortToAlmaIFBlock(
658  "core_" + mem_name + "_2nd_rdata_out", coreCount * dataWidth,
659  ProGe::OUT, lsu_prefix + "_rdata_in");
660  }
661 
662  addMemoryPorts(
663  mem_block_name + "_a", mem.mauWidth * mem.widthInMaus, mem.portAddrw,
664  mem.isShared, (mem.asAddrw == 32 && (mem.asName == PMEM_NAME)));
665  if (mem.asName == DMEM_NAME) {
666  addMemoryPorts(
667  mem_block_name + "_b", secondDmemDataw_, secondDmemAddrw_,
668  mem.isShared, false);
669  } else {
670  bool make_local_sized =
671  mem.asAddrw == 32 && (mem.asName == PMEM_NAME);
672  addMemoryPorts(
673  mem_block_name + "_b", secondPmemDataw_, secondPmemAddrw_,
674  mem.isShared, make_local_sized);
675  }
676 }

References accelInstantiator_, addMemoryPorts(), addPortToAlmaIFBlock(), almaifBlock_, MemInfo::asAddrw, MemInfo::asName, broadcast_pmem_, Environment::dataDirPath(), FileSystem::DIRECTORY_SEPARATOR, DMEM_NAME, DRAM, ProGe::IN, MemInfo::isShared, MemInfo::lsuName, MemInfo::mauWidth, ProGe::OUT, PMEM_NAME, MemInfo::portAddrw, HDLTemplateInstantiator::replacePlaceholderFromFile(), secondDmemAddrw_, secondDmemDataw_, secondDmemName_, secondPmemAddrw_, secondPmemDataw_, secondPmemName_, ProGe::NetlistBlock::setParameter(), Conversion::toString(), MemInfo::type, and MemInfo::widthInMaus.

Referenced by initAlmaifBlock().

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◆ copyPlatformFile()

void AlmaIFIntegrator::copyPlatformFile ( const TCEString  inputPath,
std::vector< TCEString > &  fileList,
bool  isScript = false 
) const
private

Definition at line 877 of file AlmaIFIntegrator.cc.

879  {
880  TCEString outputPath;
881  if (isScript) {
882  outputPath = progeFilePath(FileSystem::fileOfPath(inputPath), true);
883  } else {
884  outputPath = outputFilePath(FileSystem::fileOfPath(inputPath), true);
885  }
886 
887  FileSystem::copy(inputPath, outputPath);
888  fileList.push_back(outputPath);
889 }

References FileSystem::copy(), FileSystem::fileOfPath(), PlatformIntegrator::outputFilePath(), PlatformIntegrator::outputPath(), and PlatformIntegrator::progeFilePath().

Referenced by addAlmaifFiles().

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◆ deviceFamily()

TCEString AlmaIFIntegrator::deviceFamily ( ) const
virtual

Returns the FPGA device family

Implements PlatformIntegrator.

Definition at line 1119 of file AlmaIFIntegrator.cc.

1119  {
1120 
1121  return deviceFamily_;
1122 }

References deviceFamily_.

◆ devicePackage()

TCEString AlmaIFIntegrator::devicePackage ( ) const
virtual

Returns the device package name

Implements PlatformIntegrator.

Definition at line 1132 of file AlmaIFIntegrator.cc.

1132  {
1133  return "";
1134 }

◆ deviceSpeedClass()

TCEString AlmaIFIntegrator::deviceSpeedClass ( ) const
virtual

Returns the device speed class

Implements PlatformIntegrator.

Definition at line 1137 of file AlmaIFIntegrator.cc.

1137  {
1138  return "";
1139 }

◆ dmemInstance()

MemoryGenerator & AlmaIFIntegrator::dmemInstance ( MemInfo  dmem,
TTAMachine::FunctionUnit &  lsuArch,
std::vector< std::string >  lsuPorts 
)
protectedvirtual

Implements PlatformIntegrator.

Definition at line 1016 of file AlmaIFIntegrator.cc.

1018  {
1019  if (dmem.asName ==
1020  AXI_AS_NAME) { // AXI bus, export all ports to toplevel
1021  return *(new DummyMemGenerator(
1022  dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1023  warningStream(), errorStream()));
1024  }
1025 
1026  bool genSingleRam = false;
1027  bool genDualPortRam = false;
1028  bool overrideAsWidth = false;
1029  bool isDmem = dmem.asName == DMEM_NAME;
1030  bool isPmem = dmem.asName == PMEM_NAME;
1031  bool isSecondInstance = false;
1032 
1033  if (dmem.type == DRAM) { // AXI bus, export all ports to toplevel
1034  return *(new DummyMemGenerator(
1035  dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1036  warningStream(), errorStream()));
1037  }
1038 
1039  int bDataWidth = 0;
1040  int bAddrWidth = 0;
1041 
1042  if (isDmem || isPmem) {
1043  genDualPortRam = true;
1044  genSingleRam = dmem.isShared;
1045  if (isDmem) {
1046  if (dmemHandled_) {
1047  isSecondInstance = true;
1048  }
1049  dmem = dmemInfo_;
1050  bDataWidth = secondDmemDataw_;
1051  bAddrWidth = secondDmemAddrw_;
1052  dmemHandled_ = true;
1053  }
1054  if (isPmem) {
1055  if (pmemHandled_) {
1056  isSecondInstance = true;
1057  }
1058  dmem = pmemInfo_;
1059  bDataWidth = secondPmemDataw_;
1060  bAddrWidth = secondPmemAddrw_;
1061  pmemHandled_ = true;
1062  }
1063 
1064  // TODO: Assumes 32b wide memory (32b address - 2 mask bits)
1065  // (the AXI-lite IF also assumes this)
1066  if (dmem.asName == PMEM_NAME && dmem.asAddrw == 32) {
1067  overrideAsWidth = true;
1068  }
1069  }
1070 
1071  MemoryGenerator* memGen = NULL;
1072 
1073  if ((isSecondInstance && dmem.isShared) || dmem.type == DRAM) {
1074  memGen = new DummyMemGenerator(
1075  dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1076  warningStream(), errorStream());
1077  } else if (dmemGen_.find(dmem.asName) != dmemGen_.end()) {
1078  memGen = dmemGen_.find(dmem.asName)->second;
1079  } else {
1080  if (dmem.type == ONCHIP) {
1081  // onchip mem size is scalable, use value from adf's Address Space
1082  int addrw = dmem.portAddrw;
1083  memGen = new XilinxBlockRamGenerator(
1084  dmem.mauWidth, dmem.widthInMaus, addrw, bDataWidth,
1085  bAddrWidth, this, warningStream(), errorStream(),
1086  genDualPortRam, almaifBlock_, dmem.asName, overrideAsWidth,
1087  genSingleRam);
1088  } else {
1089  TCEString msg = "Unsupported data memory type";
1090  throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
1091  }
1092  memGen->addLsu(lsuArch, lsuPorts);
1093  dmemGen_[dmem.asName] = memGen;
1094  }
1095  return *memGen;
1096 }

References MemoryGenerator::addLsu(), almaifBlock_, MemInfo::asAddrw, MemInfo::asName, AXI_AS_NAME, DMEM_NAME, dmemGen_, dmemHandled_, dmemInfo_, DRAM, PlatformIntegrator::errorStream(), MemInfo::isShared, MemInfo::mauWidth, ONCHIP, PMEM_NAME, pmemHandled_, pmemInfo_, MemInfo::portAddrw, secondDmemAddrw_, secondDmemDataw_, secondPmemAddrw_, secondPmemDataw_, MemInfo::type, PlatformIntegrator::warningStream(), and MemInfo::widthInMaus.

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◆ exportUnconnectedPorts()

void AlmaIFIntegrator::exportUnconnectedPorts ( int  coreId)
privatevirtual

Reimplemented from PlatformIntegrator.

Definition at line 969 of file AlmaIFIntegrator.cc.

969  {
970  PlatformIntegrator::exportUnconnectedPorts(coreId);
971 
972  for (size_t i = 0; i < almaifBlock_->portCount(); i++) {
973  const NetlistPort& port = almaifBlock_->port(i);
974  if (!integratorBlock()->netlist().isPortConnected(port)) {
975  connectToplevelPort(port);
976  }
977  }
978 }

References almaifBlock_, PlatformIntegrator::connectToplevelPort(), PlatformIntegrator::exportUnconnectedPorts(), PlatformIntegrator::integratorBlock(), ProGe::NetlistBlock::port(), and ProGe::NetlistBlock::portCount().

Referenced by integrateCore().

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◆ findMemories()

void AlmaIFIntegrator::findMemories ( )
private

Definition at line 112 of file AlmaIFIntegrator.cc.

112  {
113  dmemInfo_ = pmemInfo_ = {UNKNOWN, 0, 0, 0, 0, false, "", ""};
114 
115  bool foundDmem = false;
116  bool foundPmem = false;
117 
118  // This is more or less a duplicate of parseDataMemories in the superclass
119  // to get around it not parsing memories if dmem type is 'none' and it not
120  // handling multiple lsus well
121 
122  MemInfo secondDmemInfo;
123  MemInfo secondPmemInfo;
124  TTAMachine::Machine::FunctionUnitNavigator fuNav =
125  this->machine()->functionUnitNavigator();
126  for (int i = 0; i < fuNav.count(); i++) {
127  TTAMachine::FunctionUnit* fu = fuNav.item(i);
128  if (fu->hasAddressSpace()) {
129  TTAMachine::AddressSpace* as = fu->addressSpace();
130  bool isLSU = false;
131  for (int i = 0; i < fu->operationCount(); ++i) {
132  std::string operation = fu->operation(i)->name();
133  std::string prefix = operation.substr(0, 2);
134  if (prefix == "ld" || prefix == "st") {
135  isLSU = true;
136  break;
137  }
138  }
139 
140  if (!isLSU) {
141  continue;
142  }
143 
144  if (as->name() == DMEM_NAME) {
145  if (foundDmem) {
146  assert(!secondDmem_ && "Found third DMEM LSU");
147  secondDmem_ = true;
148  secondDmemInfo = readLsuParameters(*fu);
149  if (secondDmemInfo.portAddrw < dmemInfo_.portAddrw) {
150  // Second DMEM should have lesser or equal data
151  // width => greater or equal address width
152  // swap if this is not the case
153  secondDmemInfo = dmemInfo_;
154  dmemInfo_ = readLsuParameters(*fu);
155  }
156  secondDmemName_ = secondDmemInfo.lsuName;
157  } else {
158  foundDmem = true;
159  dmemInfo_ = readLsuParameters(*fu);
160  if (dmem_dram_) {
161  dmemInfo_.type = DRAM;
162  }
163  }
164  } else if (as->name() == PMEM_NAME) {
165  if (foundPmem) {
166  assert(!secondPmem_ && "Found third PMEM LSU");
167  secondPmem_ = true;
168  secondPmemInfo = readLsuParameters(*fu);
169  } else {
170  foundPmem = true;
171  pmemInfo_ = readLsuParameters(*fu);
172 
173  // Needed for the case when the local memory doesn't exist
174  // and needs to reserved from the buffer memory
175  if (as->hasNumericalId(0)) {
176  hasSeparateLocalMemory_ = false;
177  }
178  }
179  }
180  }
181  }
182 
183  if (secondDmem_) {
184  secondDmemName_ = secondDmemInfo.lsuName;
185  secondDmemDataw_ =
186  secondDmemInfo.mauWidth * secondDmemInfo.widthInMaus;
187  secondDmemAddrw_ = secondDmemInfo.portAddrw;
188  } else if (foundDmem) {
189  secondDmemDataw_ = 32;
190  secondDmemAddrw_ = dmemInfo_.asAddrw - 2;
191  }
192 
193  if (secondPmem_) {
194  secondPmemName_ = secondPmemInfo.lsuName;
195  secondPmemDataw_ =
196  secondPmemInfo.mauWidth * secondDmemInfo.widthInMaus;
197  secondPmemAddrw_ = secondPmemInfo.portAddrw;
198  } else if (foundPmem) {
199  secondPmemDataw_ = 32;
200  secondPmemAddrw_ = pmemInfo_.asAddrw - 2;
201  }
202 }

References TTAMachine::FunctionUnit::addressSpace(), MemInfo::asAddrw, assert, TTAMachine::Machine::Navigator< ComponentType >::count(), dmem_dram_, DMEM_NAME, dmemInfo_, DRAM, TTAMachine::Machine::functionUnitNavigator(), TTAMachine::FunctionUnit::hasAddressSpace(), TTAMachine::AddressSpace::hasNumericalId(), hasSeparateLocalMemory_, TTAMachine::Machine::Navigator< ComponentType >::item(), MemInfo::lsuName, PlatformIntegrator::machine(), MemInfo::mauWidth, TTAMachine::HWOperation::name(), TTAMachine::Component::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), PMEM_NAME, pmemInfo_, MemInfo::portAddrw, PlatformIntegrator::readLsuParameters(), secondDmem_, secondDmemAddrw_, secondDmemDataw_, secondDmemName_, secondPmem_, secondPmemAddrw_, secondPmemDataw_, secondPmemName_, MemInfo::type, UNKNOWN, and MemInfo::widthInMaus.

Referenced by integrateProcessor().

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◆ imemInstance()

MemoryGenerator & AlmaIFIntegrator::imemInstance ( MemInfo  imem,
int  coreId 
)
protectedvirtual

Implements PlatformIntegrator.

Definition at line 981 of file AlmaIFIntegrator.cc.

981  {
982  assert(imem.type != UNKNOWN && "Imem type not set!");
983  int axiAddrWidth =
984  MathTools::requiredBits0Bit0(
985  (imemInfo().widthInMaus * imemInfo().mauWidth + 31) / 32 - 1) +
986  imemInfo().portAddrw;
987  if (imemGen_ == NULL) {
988  if (imem.type == ONCHIP) {
989  if (imem_dp_) {
990  imemGen_ = new XilinxBlockRamGenerator(
991  MathTools::roundUpToPowerTwo(imem.mauWidth),
992  imem.widthInMaus, imem.portAddrw,
993  MathTools::roundUpToPowerTwo(imem.mauWidth),
994  imem.portAddrw, this, warningStream(), errorStream(),
995  true, almaifBlock_, "INSTR", false, false);
996  } else {
997  imemGen_ = new XilinxBlockRamGenerator(
998  imem.mauWidth, imem.widthInMaus, imem.portAddrw, 32,
999  axiAddrWidth, this, warningStream(), errorStream(), true,
1000  almaifBlock_, "INSTR", false, false);
1001  }
1002  } else if (imem.type == VHDL_ARRAY) {
1003  imemGen_ = new VhdlRomGenerator(
1004  imem.mauWidth, imem.widthInMaus, imem.portAddrw,
1005  programName() + "_imem_pkg.vhdl", this, warningStream(),
1006  errorStream());
1007  } else if (imem.type != NONE) {
1008  TCEString msg = "Unsupported instruction memory type";
1009  throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
1010  }
1011  }
1012  return *imemGen_;
1013 }

References almaifBlock_, assert, PlatformIntegrator::errorStream(), imem_dp_, imemGen_, PlatformIntegrator::imemInfo(), MemInfo::mauWidth, NONE, ONCHIP, MemInfo::portAddrw, PlatformIntegrator::programName(), MathTools::requiredBits0Bit0(), MathTools::roundUpToPowerTwo(), MemInfo::type, UNKNOWN, VHDL_ARRAY, PlatformIntegrator::warningStream(), and MemInfo::widthInMaus.

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◆ initAlmaifBlock()

void AlmaIFIntegrator::initAlmaifBlock ( )
private

Definition at line 272 of file AlmaIFIntegrator.cc.

272  {
273  ProGe::Netlist& netlist = integratorBlock()->netlist();
274  TCEString core_count = "1";
275 
276  TCEString platformPath = Environment::dataDirPath("ProGe");
277  platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
278  << FileSystem::DIRECTORY_SEPARATOR;
279 
280  int imemdataw = imemInfo().mauWidth * imemInfo().widthInMaus;
281  int imemaddrw = imemInfo().portAddrw;
282  int imemAxiAddrw =
283  MathTools::requiredBits0Bit0((imemdataw + 31) / 32 - 1) + imemaddrw;
284  int bustrace_width = 0;
285 
286  if (imem_dp_) {
287  imemdataw = MathTools::roundUpToPowerTwo(imemdataw);
288  }
289 
290  for (int i = 0; i < machine()->busNavigator().count(); ++i) {
291  int bus_width = machine()->busNavigator().item(i)->width();
292  // Busess are padded to a multiple of 32 bits
293  bus_width = (bus_width + 31) / 32 * 32;
294  bustrace_width += bus_width;
295  }
296 
297  almaifBlock_ = new NetlistBlock(
298  ALMAIF_MODULE, ALMAIF_MODULE + "_0", integratorBlock());
299  integratorBlock()->setParameter(
300  "axi_addr_width_g", "integer", axiAddressWidth());
301  integratorBlock()->setParameter("axi_id_width_g", "integer", "12");
302  almaifBlock_->setParameter("core_count_g", "integer", core_count);
303  almaifBlock_->setParameter(
304  "axi_addr_width_g", "integer", "axi_addr_width_g");
305  almaifBlock_->setParameter("axi_id_width_g", "integer", "axi_id_width_g");
306 
307  almaifBlock_->setParameter(
308  "imem_addr_width_g", "integer", Conversion::toString(imemaddrw));
309 
310  almaifBlock_->setParameter(
311  "imem_axi_addr_width_g", "integer",
312  Conversion::toString(imemAxiAddrw));
313  if (imemInfo().type != VHDL_ARRAY) {
314  almaifBlock_->setParameter(
315  "imem_data_width_g", "integer", Conversion::toString(imemdataw));
316  } else {
317  almaifBlock_->setParameter("imem_data_width_g", "integer", "0");
318  }
319 
320  almaifBlock_->setParameter(
321  "bus_count_g", "integer", Conversion::toString(bustrace_width / 32));
322  almaifBlock_->setParameter(
323  "local_mem_addrw_g", "integer", "local_mem_addrw_g");
324 
325  // Add and connect clock and reset ports
326  NetlistPort* clk =
327  new NetlistPort("clk", "1", 1, ProGe::BIT, ProGe::IN, *almaifBlock_);
328  NetlistPort* rstx =
329  new NetlistPort("rstx", "1", 1, ProGe::BIT, ProGe::IN, *almaifBlock_);
330  netlist.connect(*clockPort(), *clk);
331  netlist.connect(*resetPort(), *rstx);
332 
333  almaifBlock_->setParameter(
334  "second_dmem_data_width_g", "integer",
335  Conversion::toString(secondDmemDataw_));
336  almaifBlock_->setParameter(
337  "second_dmem_addr_width_g", "integer",
338  Conversion::toString(secondDmemAddrw_));
339 
340  if (secondDmem_) {
341  almaifBlock_->setParameter("enable_second_dmem_g", "integer", "1");
342  accelInstantiator_.replacePlaceholderFromFile(
343  "second-dmem-port-declarations",
344  Path(platformPath + "second_dmem_port_declaration.snippet"));
345  } else {
346  almaifBlock_->setParameter("enable_second_dmem_g", "integer", "0");
347  accelInstantiator_.replacePlaceholderFromFile(
348  "second-dmem-signal-declarations",
349  Path(platformPath + "second_dmem_signal_declaration.snippet"));
350  }
351 
352  if (secondPmem_) {
353  almaifBlock_->setParameter("enable_second_pmem_g", "integer", "1");
354  accelInstantiator_.replacePlaceholderFromFile(
355  "second-pmem-port-declarations",
356  Path(platformPath + "second_pmem_port_declaration.snippet"));
357  } else {
358  almaifBlock_->setParameter("enable_second_pmem_g", "integer", "0");
359  accelInstantiator_.replacePlaceholderFromFile(
360  "second-pmem-signal-declarations",
361  Path(platformPath + "second_pmem_signal_declaration.snippet"));
362  }
363 
364  almaifBlock_->setParameter(
365  "second_pmem_data_width_g", "integer",
366  Conversion::toString(secondPmemDataw_));
367  if (pmemInfo_.asAddrw == 32) {
368  almaifBlock_->setParameter(
369  "second_pmem_addr_width_g", "integer", "local_mem_addrw_g");
370  } else {
371  almaifBlock_->setParameter(
372  "second_pmem_addr_width_g", "integer",
373  Conversion::toString(secondPmemAddrw_));
374  }
375 
376  if (syncReset_) {
377  almaifBlock_->setParameter("sync_reset_g", "integer", "1");
378  } else {
379  almaifBlock_->setParameter("sync_reset_g", "integer", "0");
380  }
381 
382  if (broadcast_pmem_) {
383  almaifBlock_->setParameter("broadcast_pmem_g", "integer", "1");
384 
385  accelInstantiator_.replacePlaceholderFromFile(
386  "pmem-bcast", Path(platformPath + "pmem_broadcast.snippet"));
387  } else {
388  almaifBlock_->setParameter("broadcast_pmem_g", "integer", "0");
389  }
390 
391  // Add AXI4 slave interface to AlmaIF block and toplevel, and connect them
392  NetlistPortGroup* axislave_almaif = axiSlavePortGroup();
393  NetlistPortGroup* axislave_ext = axislave_almaif->clone();
394  almaifBlock_->addPortGroup(axislave_almaif);
395  integratorBlock()->addPortGroup(axislave_ext);
396  netlist.connectGroupByName(*axislave_almaif, *axislave_ext);
397 
398  if (pmemInfo_.asAddrw == 32) {
399  assert(
400  broadcast_pmem_ == false &&
401  "Broadcasting pmem not supported with m_axi");
402  integratorBlock()->setParameter(
403  "local_mem_addrw_g", "integer",
404  Conversion::toString(DEFAULT_LOCAL_MEMORY_WIDTH - 2));
405 
406  integratorBlock()->setParameter(
407  "axi_offset_low_g", "integer", "1136656384");
408  integratorBlock()->setParameter("axi_offset_high_g", "integer", "0");
409  almaifBlock_->setParameter(
410  "axi_offset_low_g", "integer", "axi_offset_low_g");
411  almaifBlock_->setParameter(
412  "axi_offset_high_g", "integer", "axi_offset_high_g");
413 
414  NetlistPortGroup* aximaster_almaif = axiMasterPortGroup();
415  NetlistPortGroup* aximaster_ext = aximaster_almaif->clone();
416  almaifBlock_->addPortGroup(aximaster_almaif);
417  integratorBlock()->addPortGroup(aximaster_ext);
418  netlist.connectGroupByName(*aximaster_almaif, *aximaster_ext);
419  } else {
420  integratorBlock()->setParameter(
421  "local_mem_addrw_g", "integer",
422  Conversion::toString(pmemInfo_.portAddrw));
423  almaifBlock_->setParameter("axi_offset_low_g", "integer", "0");
424  almaifBlock_->setParameter(
425  "axi_offset_high_g", "integer", "0");
426  }
427 
428  int coreCount = 1;
429  // Debug signals
430  if (!hasMinimalDebugger_) {
431  almaifBlock_->setParameter("full_debugger_g", "integer", "1");
432  accelInstantiator_.replacePlaceholderFromFile(
433  "full-debugger-port-declarations",
434  Path(platformPath + "full_debugger_port_declaration.snippet"));
435  accelInstantiator_.replacePlaceholderFromFile(
436  "debugger", Path(platformPath + "full_debugger.snippet"));
437 
438  addPortToAlmaIFBlock(
439  "core_db_pc_start", coreCount * imemaddrw, ProGe::OUT,
440  "db_pc_start");
441  addPortToAlmaIFBlock(
442  "core_db_pc_next", coreCount * imemaddrw, ProGe::IN,
443  "db_pc_next");
444  addPortToAlmaIFBlock(
445  "core_db_bustraces", coreCount * bustrace_width, ProGe::IN,
446  "db_bustraces");
447  } else {
448  almaifBlock_->setParameter("full_debugger_g", "integer", "0");
449  accelInstantiator_.replacePlaceholderFromFile(
450  "mini-debugger-signal-declarations",
451  Path(platformPath + "mini_debugger_signal_declaration.snippet"));
452  accelInstantiator_.replacePlaceholderFromFile(
453  "debugger", Path(platformPath + "mini_debugger.snippet"));
454  }
455 
456  // Set the default value in case when there is no separate scratchpad memory.
457  // AlmaIF interface must reserve some part of the global buffer memory
458  // (pmem) and communicate that in the interface
459  if (!hasSeparateLocalMemory_) {
460  almaifBlock_->setParameter(
461  "reserved_sp_bytes_g", "integer",
462  Conversion::toString(DEFAULT_RESERVED_PRIVATE_MEM_SIZE));
463  }
464 
465  addPortToAlmaIFBlock(
466  "core_db_pc", coreCount * imemaddrw, ProGe::IN, "db_pc");
467  addPortToAlmaIFBlock(
468  "core_db_lockcnt", coreCount * 64, ProGe::IN, "db_lockcnt");
469  addPortToAlmaIFBlock(
470  "core_db_cyclecnt", coreCount * 64, ProGe::IN, "db_cyclecnt");
471  addPortToAlmaIFBlock(
472  "core_db_tta_nreset", coreCount, ProGe::OUT, "db_tta_nreset");
473  addPortToAlmaIFBlock(
474  "core_db_lockrq", coreCount, ProGe::OUT, "db_lockrq");
475  if (dmem_dram_) {
476  addPortToAlmaIFBlock(
477  "core_db_dram_offset", 32, ProGe::OUT, "db_dram_offset");
478  accelInstantiator_.replacePlaceholder(
479  "dram-offset-port-declaration",
480  "core_db_dram_offset : out std_logic_vector(32-1 downto 0);");
481  // We want to disable dmem from tta-accel, because dmem exists in dram
482  accelInstantiator_.replacePlaceholder(
483  "enable-dmem", "constant enable_dmem : boolean := false;");
484  } else {
485  // Dummy signal to connect to not leave minidebuggers portmap
486  // undefined
487  accelInstantiator_.replacePlaceholder(
488  "dram-offset-dummy-declaration",
489  "signal core_db_dram_offset : std_logic_vector(32-1 downto 0);");
490  accelInstantiator_.replacePlaceholder(
491  "enable-dmem",
492  "constant enable_dmem : boolean := dmem_data_width_g > 0;");
493  }
494 
495  if (imemInfo().type != VHDL_ARRAY) {
496  // Ifetch signals
497  addPortToAlmaIFBlock("core_busy_out", coreCount, ProGe::OUT, "busy");
498  addPortToAlmaIFBlock(
499  "core_imem_data_out", coreCount * imemdataw, ProGe::OUT,
500  "imem_data");
501  addPortToAlmaIFBlock(
502  "core_imem_en_x_in", coreCount, ProGe::IN, "imem_en_x");
503  addPortToAlmaIFBlock(
504  "core_imem_addr_in", coreCount * imemaddrw, ProGe::IN,
505  "imem_addr");
506 
507  if (imem_dp_) {
508  const int strb_width = imemdataw / 8;
509  const int half_cores_ceil = (coreCount + 1) / 2;
510  // Dualport memories have identical a-b ports, except with odd
511  // corecounts the b is full and the a's msb-side is unconnected
512  addMemoryPorts(
513  "INSTR_a", half_cores_ceil, imemdataw * half_cores_ceil,
514  imemaddrw * half_cores_ceil, strb_width * half_cores_ceil,
515  false);
516  addMemoryPorts(
517  "INSTR_b", half_cores_ceil, imemdataw * half_cores_ceil,
518  imemaddrw * half_cores_ceil, strb_width * half_cores_ceil,
519  false);
520  } else {
521  addMemoryPorts("INSTR_a", imemdataw, imemaddrw, false, false);
522  addMemoryPorts("INSTR_b", 32, imemAxiAddrw, false, false);
523  }
524  TCEString platformPath = Environment::dataDirPath("ProGe");
525  platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
526  << FileSystem::DIRECTORY_SEPARATOR;
527 
528  accelInstantiator_.replacePlaceholderFromFile(
529  "imem-statements",
530  Path(platformPath + "imem_statements.snippet"));
531  if (imem_dp_) {
532  accelInstantiator_.replacePlaceholderFromFile(
533  "imem-bcast",
534  Path(platformPath + "imem_broadcast_dualport.snippet"));
535  accelInstantiator_.replacePlaceholderFromFile(
536  "imem-port-declarations",
537  Path(
538  platformPath + "imem_port_declaration_dualport.snippet"));
539  } else {
540  accelInstantiator_.replacePlaceholderFromFile(
541  "imem-bcast", Path(platformPath + "imem_broadcast.snippet"));
542  accelInstantiator_.replacePlaceholderFromFile(
543  "imem-port-declarations",
544  Path(platformPath + "imem_port_declaration.snippet"));
545  }
546  }
547 
548  connectCoreMemories(dmemInfo_, "dmem", "data", secondDmem_);
549  connectCoreMemories(pmemInfo_, "pmem", "param", secondPmem_);
550 }

References accelInstantiator_, addMemoryPorts(), ProGe::NetlistBlock::addPortGroup(), addPortToAlmaIFBlock(), ALMAIF_MODULE, almaifBlock_, MemInfo::asAddrw, assert, axiAddressWidth(), axiMasterPortGroup(), axiSlavePortGroup(), ProGe::BIT, broadcast_pmem_, TTAMachine::Machine::busNavigator(), PlatformIntegrator::clockPort(), ProGe::NetlistPortGroup::clone(), ProGe::Netlist::connect(), connectCoreMemories(), ProGe::Netlist::connectGroupByName(), TTAMachine::Machine::Navigator< ComponentType >::count(), Environment::dataDirPath(), DEFAULT_LOCAL_MEMORY_WIDTH, DEFAULT_RESERVED_PRIVATE_MEM_SIZE, FileSystem::DIRECTORY_SEPARATOR, dmem_dram_, dmemInfo_, hasMinimalDebugger_, hasSeparateLocalMemory_, imem_dp_, PlatformIntegrator::imemInfo(), ProGe::IN, PlatformIntegrator::integratorBlock(), TTAMachine::Machine::Navigator< ComponentType >::item(), PlatformIntegrator::machine(), MemInfo::mauWidth, ProGe::NetlistBlock::netlist(), ProGe::OUT, pmemInfo_, MemInfo::portAddrw, HDLTemplateInstantiator::replacePlaceholder(), HDLTemplateInstantiator::replacePlaceholderFromFile(), MathTools::requiredBits0Bit0(), PlatformIntegrator::resetPort(), MathTools::roundUpToPowerTwo(), secondDmem_, secondDmemAddrw_, secondDmemDataw_, secondPmem_, secondPmemAddrw_, secondPmemDataw_, ProGe::NetlistBlock::setParameter(), syncReset_, Conversion::toString(), VHDL_ARRAY, and MemInfo::widthInMaus.

Referenced by integrateProcessor().

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◆ integrateCore()

bool AlmaIFIntegrator::integrateCore ( const ProGe::NetlistBlock &  cores,
int  coreId 
)
virtual

Integrates a single TTA core

Parameters
coresNetlistBlock containing the core(s)
coreIdIndex of the core to be integrated

Reimplemented from PlatformIntegrator.

Definition at line 892 of file AlmaIFIntegrator.cc.

892  {
893  ProGe::Netlist& netlist = integratorBlock()->netlist();
894 
895  TCEString clkPortName = PlatformIntegrator::TTA_CORE_CLK;
896  TCEString resetPortName = PlatformIntegrator::TTA_CORE_RSTX;
897 
898  if (!createMemories(coreId)) {
899  return false;
900  }
901 
902  // Connect cycle count, stall count ports if needed by an FU
903  auto ttaCCPort = core.port("debug_cycle_count_in");
904  if (ttaCCPort) {
905  netlist.connect(*core.port("db_cyclecnt"), *ttaCCPort);
906  }
907  auto ttaLCPort = core.port("debug_lock_count_in");
908  if (ttaLCPort) {
909  netlist.connect(*core.port("db_lockcnt"), *ttaLCPort);
910  }
911  for (size_t i = 0; i < core.portCount(); ++i) {
912  TCEString portName = core.port(i).name();
913 
914  // Connect global clock and reset ports
915  if (portName == PlatformIntegrator::TTA_CORE_CLK) {
916  netlist.connect(*clockPort(), core.port(i));
917  } else if (portName == PlatformIntegrator::TTA_CORE_RSTX) {
918  netlist.connect(*resetPort(), core.port(i));
919  } else {
920  // Strip coreN_ -prefix for multicore TTAs
921  if (portName.substr(0, 4) == "core") {
922  TCEString coreKey;
923  coreKey << "core" << coreId;
924  size_t cutoff = portName.find_first_of('_');
925  if (portName.substr(0, cutoff) != coreKey) {
926  // Port doesn't belong to core, skip
927  continue;
928  }
929  portName = portName.substr(cutoff + 1);
930  }
931  if (almaif_ttacore_ports.find(portName) !=
932  almaif_ttacore_ports.end()) {
933  int portWidth = almaif_ttacore_ports[portName]->realWidth();
934 
935  // Connect AlmaIF block to TTA
936 
937  if (coreId != -1 && imem_dp_ && portName == "imem_data") {
938  // imem_dp_ works with padded imem data signals. So here
939  // we connect only the real bits, but with padded
940  // differences.
941  netlist.connect(
942  core.port(i), *almaif_ttacore_ports[portName], 0,
943  portWidth * coreId, imemInfo().mauWidth);
944 
945  } else if (coreId != -1) {
946  netlist.connect(
947  core.port(i), *almaif_ttacore_ports[portName], 0,
948  portWidth * coreId, portWidth);
949  } else {
950  netlist.connect(
951  core.port(i), *almaif_ttacore_ports[portName]);
952  }
953  } else if (
954  dmem_dram_ &&
955  portName ==
956  (boost::format("fu_%s_dram_offset") % dmemInfo_.lsuName)
957  .str()) {
958  netlist.connect(
959  core.port(i), *almaifBlock_->port("db_dram_offset"));
960  }
961  }
962  }
963 
964  exportUnconnectedPorts(coreId);
965  return true;
966 }

References almaif_ttacore_ports, almaifBlock_, PlatformIntegrator::clockPort(), ProGe::Netlist::connect(), PlatformIntegrator::createMemories(), dmem_dram_, dmemInfo_, exportUnconnectedPorts(), imem_dp_, PlatformIntegrator::imemInfo(), PlatformIntegrator::integratorBlock(), MemInfo::lsuName, ProGe::NetlistPort::name(), ProGe::NetlistBlock::netlist(), ProGe::NetlistBlock::port(), ProGe::NetlistBlock::portCount(), PlatformIntegrator::resetPort(), PlatformIntegrator::TTA_CORE_CLK, and PlatformIntegrator::TTA_CORE_RSTX.

Referenced by integrateProcessor().

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◆ integrateProcessor()

void AlmaIFIntegrator::integrateProcessor ( const ProGe::NetlistBlock *  progeBlock)
virtual

Integrates the TTA core(s) generated by ProGe

Parameters
progeBlockThe toplevel netlist block created by ProGe

Implements PlatformIntegrator.

Definition at line 205 of file AlmaIFIntegrator.cc.

206  {
207 
208  initPlatformNetlist(progeBlockInOldNetlist);
209  findMemories();
210  initAlmaifBlock();
211  const NetlistBlock& cores = progeBlock();
212  int coreCount = 1;
213  for (int i = 0; i < coreCount; i++) {
214  int coreId = coreCount == 1 ? -1 : i;
215  if (!integrateCore(cores, coreId)) {
216  return;
217  }
218  }
219 
220  writeNewToplevel();
221 
222  addAlmaifFiles();
223  addProGeFiles();
224 
225  projectFileGenerator()->writeProjectFiles();
226 }

References addAlmaifFiles(), PlatformIntegrator::addProGeFiles(), findMemories(), initAlmaifBlock(), PlatformIntegrator::initPlatformNetlist(), integrateCore(), PlatformIntegrator::progeBlock(), projectFileGenerator(), PlatformIntegrator::writeNewToplevel(), and ProjectFileGenerator::writeProjectFiles().

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◆ pinTag()

TCEString AlmaIFIntegrator::pinTag ( ) const
virtual

Implements PlatformIntegrator.

Definition at line 1147 of file AlmaIFIntegrator.cc.

1147  {
1148  return "";
1149 }

◆ printInfo()

void AlmaIFIntegrator::printInfo ( std::ostream &  stream) const
virtual

Prints information about the platform

Implements PlatformIntegrator.

Definition at line 1099 of file AlmaIFIntegrator.cc.

1099  {
1100  stream
1101  << "Integrator name: AlmaIFIntegrator" << std::endl
1102  << "-----------------------------" << std::endl
1103  << "Integrates the processor core to an AXI4 bus interface according "
1104  << "to ALMARVI HW Integration Interface specification." << std::endl
1105  << "Supported instruction memory types are 'onchip' and 'none'."
1106  << std::endl
1107  << "Supported data memory types are 'onchip' and 'none'." << std::endl
1108  << "Data and Parameter memory spaces must be named '" << DMEM_NAME
1109  << "' and '" << PMEM_NAME << "' respectively." << std::endl
1110  << std::endl;
1111 }

References DMEM_NAME, and PMEM_NAME.

◆ projectFileGenerator()

ProjectFileGenerator * AlmaIFIntegrator::projectFileGenerator ( ) const
virtual

Implements PlatformIntegrator.

Definition at line 1152 of file AlmaIFIntegrator.cc.

1152  {
1153  return fileGen_;
1154 }

References fileGen_.

Referenced by addAlmaifFiles(), and integrateProcessor().

◆ setDeviceFamily()

void AlmaIFIntegrator::setDeviceFamily ( TCEString  devFamily)
virtual

Set the FPGA device family.

Intended for TTA IP integration. Integrator can device whether this overrides the default device family.

Implements PlatformIntegrator.

Definition at line 1125 of file AlmaIFIntegrator.cc.

1125  {
1126 
1127  deviceFamily_ = devFamily;
1128 }

References deviceFamily_.

◆ targetClockFrequency()

int AlmaIFIntegrator::targetClockFrequency ( ) const
virtual

Returns the target clock frequency in MHz

Reimplemented from PlatformIntegrator.

Definition at line 1142 of file AlmaIFIntegrator.cc.

1142  {
1143  return 1;
1144 }

Member Data Documentation

◆ accelInstantiator_

HDLTemplateInstantiator AlmaIFIntegrator::accelInstantiator_
private

Definition at line 149 of file AlmaIFIntegrator.hh.

Referenced by addAlmaifFiles(), connectCoreMemories(), and initAlmaifBlock().

◆ ALMAIF_MODULE

const TCEString AlmaIFIntegrator::ALMAIF_MODULE = "tta_accel"
staticprivate

Definition at line 123 of file AlmaIFIntegrator.hh.

Referenced by initAlmaifBlock().

◆ almaif_ttacore_ports

std::map<TCEString, ProGe::NetlistPort*> AlmaIFIntegrator::almaif_ttacore_ports
private

Definition at line 131 of file AlmaIFIntegrator.hh.

Referenced by addPortToAlmaIFBlock(), and integrateCore().

◆ almaifBlock_

ProGe::NetlistBlock* AlmaIFIntegrator::almaifBlock_
private

Definition at line 133 of file AlmaIFIntegrator.hh.

Referenced by addPortToAlmaIFBlock(), connectCoreMemories(), dmemInstance(), exportUnconnectedPorts(), imemInstance(), initAlmaifBlock(), and integrateCore().

◆ AXI_AS_NAME

const TCEString AlmaIFIntegrator::AXI_AS_NAME = "axi_as"
staticprivate

Definition at line 122 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance().

◆ broadcast_pmem_

bool AlmaIFIntegrator::broadcast_pmem_
private

Definition at line 154 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), and initAlmaifBlock().

◆ DEFAULT_DEVICE

const TCEString AlmaIFIntegrator::DEFAULT_DEVICE = "xc7z020clg400-1"
staticprivate

Definition at line 124 of file AlmaIFIntegrator.hh.

◆ DEFAULT_LOCAL_MEMORY_WIDTH

const int AlmaIFIntegrator::DEFAULT_LOCAL_MEMORY_WIDTH = 12
staticprivate

Definition at line 127 of file AlmaIFIntegrator.hh.

Referenced by axiAddressWidth(), and initAlmaifBlock().

◆ DEFAULT_RESERVED_PRIVATE_MEM_SIZE

const int AlmaIFIntegrator::DEFAULT_RESERVED_PRIVATE_MEM_SIZE = 2048
staticprivate

Definition at line 126 of file AlmaIFIntegrator.hh.

Referenced by initAlmaifBlock().

◆ deviceFamily_

TCEString AlmaIFIntegrator::deviceFamily_
private

Definition at line 135 of file AlmaIFIntegrator.hh.

Referenced by deviceFamily(), and setDeviceFamily().

◆ deviceName_

TCEString AlmaIFIntegrator::deviceName_
private

Definition at line 136 of file AlmaIFIntegrator.hh.

◆ dmem_dram_

bool AlmaIFIntegrator::dmem_dram_ = false
private

Definition at line 155 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), initAlmaifBlock(), and integrateCore().

◆ DMEM_NAME

const TCEString AlmaIFIntegrator::DMEM_NAME = "data"
staticprivate

Definition at line 120 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and printInfo().

◆ dmemGen_

std::map<TCEString, MemoryGenerator*> AlmaIFIntegrator::dmemGen_
private

Definition at line 130 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance(), and ~AlmaIFIntegrator().

◆ dmemHandled_

bool AlmaIFIntegrator::dmemHandled_
private

Definition at line 143 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance().

◆ dmemInfo_

MemInfo AlmaIFIntegrator::dmemInfo_
private

Definition at line 140 of file AlmaIFIntegrator.hh.

Referenced by axiAddressWidth(), dmemInstance(), findMemories(), initAlmaifBlock(), and integrateCore().

◆ fileGen_

DefaultProjectFileGenerator* AlmaIFIntegrator::fileGen_
private

Definition at line 138 of file AlmaIFIntegrator.hh.

Referenced by projectFileGenerator().

◆ hasMinimalDebugger_

bool AlmaIFIntegrator::hasMinimalDebugger_
private

Definition at line 151 of file AlmaIFIntegrator.hh.

Referenced by addAlmaifFiles(), AlmaIFIntegrator(), and initAlmaifBlock().

◆ hasSeparateLocalMemory_

bool AlmaIFIntegrator::hasSeparateLocalMemory_ = true
private

Definition at line 152 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), and initAlmaifBlock().

◆ imem_dp_

bool AlmaIFIntegrator::imem_dp_ = false
private

Definition at line 156 of file AlmaIFIntegrator.hh.

Referenced by imemInstance(), initAlmaifBlock(), and integrateCore().

◆ imemGen_

MemoryGenerator* AlmaIFIntegrator::imemGen_
private

Definition at line 129 of file AlmaIFIntegrator.hh.

Referenced by imemInstance(), and ~AlmaIFIntegrator().

◆ PMEM_NAME

const TCEString AlmaIFIntegrator::PMEM_NAME = "param"
staticprivate

Definition at line 121 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and printInfo().

◆ pmemHandled_

bool AlmaIFIntegrator::pmemHandled_
private

Definition at line 143 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance().

◆ pmemInfo_

MemInfo AlmaIFIntegrator::pmemInfo_
private

Definition at line 140 of file AlmaIFIntegrator.hh.

Referenced by addAlmaifFiles(), axiAddressWidth(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondDmem_

bool AlmaIFIntegrator::secondDmem_
private

Definition at line 142 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), and initAlmaifBlock().

◆ secondDmemAddrw_

int AlmaIFIntegrator::secondDmemAddrw_ = 0
private

Definition at line 146 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondDmemDataw_

int AlmaIFIntegrator::secondDmemDataw_ = 0
private

Definition at line 145 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondDmemName_

std::string AlmaIFIntegrator::secondDmemName_
private

Definition at line 144 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), and findMemories().

◆ secondPmem_

bool AlmaIFIntegrator::secondPmem_
private

Definition at line 142 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), and initAlmaifBlock().

◆ secondPmemAddrw_

int AlmaIFIntegrator::secondPmemAddrw_
private

Definition at line 148 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondPmemDataw_

int AlmaIFIntegrator::secondPmemDataw_
private

Definition at line 148 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondPmemName_

std::string AlmaIFIntegrator::secondPmemName_
private

Definition at line 147 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), and findMemories().

◆ syncReset_

bool AlmaIFIntegrator::syncReset_
private

Definition at line 153 of file AlmaIFIntegrator.hh.

Referenced by initAlmaifBlock().

The documentation for this class was generated from the following files:
XilinxBlockRamGenerator
Definition: XilinxBlockRamGenerator.hh:41
AlmaIFIntegrator::accelInstantiator_
HDLTemplateInstantiator accelInstantiator_
Definition: AlmaIFIntegrator.hh:149
PlatformIntegrator::TTA_CORE_RSTX
static const TCEString TTA_CORE_RSTX
Definition: PlatformIntegrator.hh:304
PlatformIntegrator::initPlatformNetlist
virtual void initPlatformNetlist(const ProGe::NetlistBlock *progeBlock)
Definition: PlatformIntegrator.cc:317
ProGe::NetlistBlock::netlist
virtual const Netlist & netlist() const
Definition: BaseNetlistBlock.cc:348
ProGe::NetlistPortGroup::clone
virtual NetlistPortGroup * clone(bool asMirrored=false) const
Definition: NetlistPortGroup.cc:169
AlmaIFIntegrator::DEFAULT_LOCAL_MEMORY_WIDTH
static const int DEFAULT_LOCAL_MEMORY_WIDTH
Definition: AlmaIFIntegrator.hh:127
Path
Definition: FileSystem.hh:197
AlmaIFIntegrator::AXI_AS_NAME
static const TCEString AXI_AS_NAME
Definition: AlmaIFIntegrator.hh:122
PlatformIntegrator::clockPort
ProGe::NetlistPort * clockPort() const
Definition: PlatformIntegrator.cc:692
PlatformIntegrator::coreEntityName
TCEString coreEntityName() const
Definition: PlatformIntegrator.cc:126
TTAMachine::Component::name
virtual TCEString name() const
Definition: MachinePart.cc:125
ProGe::NetlistBlock
Definition: NetlistBlock.hh:61
AlmaIFIntegrator::hasSeparateLocalMemory_
bool hasSeparateLocalMemory_
Definition: AlmaIFIntegrator.hh:152
TTAMachine::FunctionUnit::hasAddressSpace
virtual bool hasAddressSpace() const
Definition: FunctionUnit.cc:608
AlmaIFIntegrator::axiMasterPortGroup
ProGe::NetlistPortGroup * axiMasterPortGroup()
Definition: AlmaIFIntegrator.cc:753
TTAMachine::AddressSpace
Definition: AddressSpace.hh:51
AlmaIFIntegrator::secondDmemName_
std::string secondDmemName_
Definition: AlmaIFIntegrator.hh:144
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
MemInfo
Definition: MemoryGenerator.hh:67
TTAMachine::AddressSpace::hasNumericalId
virtual bool hasNumericalId(unsigned id) const
Definition: AddressSpace.cc:383
PlatformIntegrator::deviceName
TCEString deviceName() const
Definition: PlatformIntegrator.hh:114
AlmaIFIntegrator::secondPmemAddrw_
int secondPmemAddrw_
Definition: AlmaIFIntegrator.hh:148
AlmaIFIntegrator::dmem_dram_
bool dmem_dram_
Definition: AlmaIFIntegrator.hh:155
AlmaIFIntegrator::syncReset_
bool syncReset_
Definition: AlmaIFIntegrator.hh:153
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void setParameter(const std::string &name, const std::string &type, const std::string &value)
Definition: NetlistBlock.cc:89
PlatformIntegrator::TTA_CORE_CLK
static const TCEString TTA_CORE_CLK
Definition: PlatformIntegrator.hh:303
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virtual AddressSpace * addressSpace() const
Definition: FunctionUnit.cc:580
PlatformIntegrator::writeNewToplevel
virtual void writeNewToplevel()
Definition: PlatformIntegrator.cc:609
AlmaIFIntegrator::secondDmemAddrw_
int secondDmemAddrw_
Definition: AlmaIFIntegrator.hh:146
ProjectFileGenerator::writeProjectFiles
virtual void writeProjectFiles()=0
AlmaIFIntegrator::secondPmemDataw_
int secondPmemDataw_
Definition: AlmaIFIntegrator.hh:148
TTAMachine::Machine::Navigator::count
int count() const
ProGe::Netlist
Definition: Netlist.hh:63
PlatformIntegrator::createMemories
virtual bool createMemories(int coreId)
Definition: PlatformIntegrator.cc:542
FileSystem::fileOfPath
static std::string fileOfPath(const std::string pathName)
Definition: FileSystem.cc:101
Conversion::toString
static std::string toString(const T &source)
ProGe::NetlistBlock::portCount
virtual size_t portCount() const
Definition: BaseNetlistBlock.cc:248
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void replacePlaceholderFromFile(const std::string &key, const Path &filePath, bool append=false)
Definition: HDLTemplateInstantiator.cc:89
DummyMemGenerator
Definition: DummyMemGenerator.hh:43
ProGe::Netlist::connect
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
Definition: Netlist.cc:83
ProGe::Netlist::connectGroupByName
bool connectGroupByName(const NetlistPortGroup &group1, const NetlistPortGroup &group2)
Definition: Netlist.cc:238
DRAM
@ DRAM
Definition: MemoryGenerator.hh:63
PlatformIntegrator::outputPath
TCEString outputPath() const
Definition: PlatformIntegrator.cc:179
PlatformIntegrator::connectToplevelPort
virtual void connectToplevelPort(const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")
Definition: PlatformIntegrator.cc:464
AlmaIFIntegrator::secondDmemDataw_
int secondDmemDataw_
Definition: AlmaIFIntegrator.hh:145
ProGe::SignalGroup
Definition: SignalGroup.hh:48
assert
#define assert(condition)
Definition: Application.hh:86
TTAMachine::FunctionUnit
Definition: FunctionUnit.hh:55
IDF::MachineImplementation::icDecoderParameterValue
std::string icDecoderParameterValue(const std::string &name) const
Definition: MachineImplementation.cc:1415
AlmaIFIntegrator::findMemories
void findMemories()
Definition: AlmaIFIntegrator.cc:112
AlmaIFIntegrator::pmemInfo_
MemInfo pmemInfo_
Definition: AlmaIFIntegrator.hh:140
AlmaIFIntegrator::axiAddressWidth
TCEString axiAddressWidth() const
Definition: AlmaIFIntegrator.cc:237
ProGe::NetlistPortGroup
Definition: NetlistPortGroup.hh:53
TTAMachine::HWOperation::name
const std::string & name() const
Definition: HWOperation.cc:141
MemInfo::type
MemType type
Definition: MemoryGenerator.hh:68
InvalidData
Definition: Exception.hh:149
PlatformIntegrator::resetPort
ProGe::NetlistPort * resetPort() const
Definition: PlatformIntegrator.cc:704
MemInfo::asAddrw
int asAddrw
Definition: MemoryGenerator.hh:72
AlmaIFIntegrator::broadcast_pmem_
bool broadcast_pmem_
Definition: AlmaIFIntegrator.hh:154
MemInfo::asName
TCEString asName
Definition: MemoryGenerator.hh:74
PlatformIntegrator::progeBlock
const ProGe::NetlistBlock & progeBlock() const
Definition: PlatformIntegrator.cc:530
AlmaIFIntegrator::axiSlavePortGroup
ProGe::NetlistPortGroup * axiSlavePortGroup()
Definition: AlmaIFIntegrator.cc:714
AlmaIFIntegrator::almaif_ttacore_ports
std::map< TCEString, ProGe::NetlistPort * > almaif_ttacore_ports
Definition: AlmaIFIntegrator.hh:131
TTAMachine::Machine::functionUnitNavigator
virtual FunctionUnitNavigator functionUnitNavigator() const
Definition: Machine.cc:380
AlmaIFIntegrator::imem_dp_
bool imem_dp_
Definition: AlmaIFIntegrator.hh:156
PlatformIntegrator::PlatformIntegrator
PlatformIntegrator()
Definition: PlatformIntegrator.cc:68
PlatformIntegrator::idf
const IDF::MachineImplementation * idf() const
Definition: PlatformIntegrator.cc:304
FileSystem::copy
static void copy(const std::string &source, const std::string &target)
Definition: FileSystem.cc:524
ProGe::NetlistPortGroup::addPort
void addPort(NetlistPort &port)
Definition: NetlistPortGroup.cc:93
AlmaIFIntegrator::addPortToAlmaIFBlock
void addPortToAlmaIFBlock(const TCEString name, const TCEString width, const ProGe::Direction dir, const TCEString core_name="")
Definition: AlmaIFIntegrator.cc:679
AlmaIFIntegrator::dmemInfo_
MemInfo dmemInfo_
Definition: AlmaIFIntegrator.hh:140
TTAMachine::FunctionUnit::operationCount
virtual int operationCount() const
Definition: FunctionUnit.cc:419
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
AlmaIFIntegrator::addPortToGroup
void addPortToGroup(ProGe::NetlistPortGroup *port_group, const ProGe::Direction dir, const TCEString name, const TCEString width)
Definition: AlmaIFIntegrator.cc:698
AlmaIFIntegrator::dmemHandled_
bool dmemHandled_
Definition: AlmaIFIntegrator.hh:143
PlatformIntegrator::machine
const TTAMachine::Machine * machine() const
Definition: PlatformIntegrator.cc:297
MemoryGenerator::addLsu
void addLsu(TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition: MemoryGenerator.cc:376
AlmaIFIntegrator::deviceFamily_
TCEString deviceFamily_
Definition: AlmaIFIntegrator.hh:135
MemInfo::widthInMaus
int widthInMaus
Definition: MemoryGenerator.hh:70
VhdlRomGenerator
Definition: VhdlRomGenerator.hh:42
PlatformIntegrator::imemInfo
const MemInfo & imemInfo() const
Definition: PlatformIntegrator.cc:651
MemInfo::mauWidth
int mauWidth
Definition: MemoryGenerator.hh:69
AlmaIFIntegrator::connectCoreMemories
void connectCoreMemories(MemInfo mem, TCEString mem_name, TCEString mem_block_name, bool seconds)
Definition: AlmaIFIntegrator.cc:553
AlmaIFIntegrator::PMEM_NAME
static const TCEString PMEM_NAME
Definition: AlmaIFIntegrator.hh:121
ProjectFileGenerator::addHdlFile
void addHdlFile(const TCEString &file)
Definition: ProjectFileGenerator.cc:56
AlmaIFIntegrator::exportUnconnectedPorts
void exportUnconnectedPorts(int coreId)
Definition: AlmaIFIntegrator.cc:969
AlmaIFIntegrator::addMemoryPorts
void addMemoryPorts(const TCEString as_name, int data_width, int addr_width, const bool isShared, const bool overrideAsWidth)
Definition: AlmaIFIntegrator.cc:778
AlmaIFIntegrator::addAlmaifFiles
void addAlmaifFiles()
Definition: AlmaIFIntegrator.cc:817
FileSystem::DIRECTORY_SEPARATOR
static const std::string DIRECTORY_SEPARATOR
Definition: FileSystem.hh:189
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
AlmaIFIntegrator::secondPmem_
bool secondPmem_
Definition: AlmaIFIntegrator.hh:142
NONE
@ NONE
Definition: MemoryGenerator.hh:59
DefaultProjectFileGenerator
Definition: DefaultProjectFileGenerator.hh:43
AlmaIFIntegrator::copyPlatformFile
void copyPlatformFile(const TCEString inputPath, std::vector< TCEString > &fileList, bool isScript=false) const
Definition: AlmaIFIntegrator.cc:877
MemInfo::isShared
bool isShared
Definition: MemoryGenerator.hh:73
PlatformIntegrator::integratorBlock
ProGe::NetlistBlock * integratorBlock()
Definition: PlatformIntegrator.cc:291
PlatformIntegrator::programName
TCEString programName() const
Definition: PlatformIntegrator.cc:133
HDLTemplateInstantiator::replacePlaceholder
void replacePlaceholder(const std::string &key, const std::string &replacer, bool append=false)
Definition: HDLTemplateInstantiator.cc:62
PlatformIntegrator::exportUnconnectedPorts
virtual void exportUnconnectedPorts(int coreId)
Definition: PlatformIntegrator.cc:453
ONCHIP
@ ONCHIP
Definition: MemoryGenerator.hh:61
PlatformIntegrator::progeFilePath
TCEString progeFilePath(TCEString fileName, bool absolute=false) const
Definition: PlatformIntegrator.cc:140
PlatformIntegrator::readLsuParameters
MemInfo readLsuParameters(const TTAMachine::FunctionUnit &lsu)
Definition: PlatformIntegrator.cc:403
AlmaIFIntegrator::imemGen_
MemoryGenerator * imemGen_
Definition: AlmaIFIntegrator.hh:129
AlmaIFIntegrator::DEFAULT_RESERVED_PRIVATE_MEM_SIZE
static const int DEFAULT_RESERVED_PRIVATE_MEM_SIZE
Definition: AlmaIFIntegrator.hh:126
ProGe::DataType
DataType
Data types of hardware ports.
Definition: ProGeTypes.hh:46
AlmaIFIntegrator::initAlmaifBlock
void initAlmaifBlock()
Definition: AlmaIFIntegrator.cc:272
TCEString
Definition: TCEString.hh:53
PlatformIntegrator::warningStream
std::ostream & warningStream() const
Definition: PlatformIntegrator.cc:271
UNKNOWN
@ UNKNOWN
Definition: MemoryGenerator.hh:58
AlmaIFIntegrator::ALMAIF_MODULE
static const TCEString ALMAIF_MODULE
Definition: AlmaIFIntegrator.hh:123
TTAMachine::Machine::busNavigator
virtual BusNavigator busNavigator() const
Definition: Machine.cc:356
VHDL_ARRAY
@ VHDL_ARRAY
Definition: MemoryGenerator.hh:60
AlmaIFIntegrator::hasMinimalDebugger_
bool hasMinimalDebugger_
Definition: AlmaIFIntegrator.hh:151
ProGe::NetlistBlock::addPortGroup
void addPortGroup(NetlistPortGroup *portGroup)
Definition: BaseNetlistBlock.cc:508
ProGe::NetlistPort
Definition: NetlistPort.hh:70
MathTools::roundUpToPowerTwo
static unsigned int roundUpToPowerTwo(unsigned int number)
AlmaIFIntegrator::dmemGen_
std::map< TCEString, MemoryGenerator * > dmemGen_
Definition: AlmaIFIntegrator.hh:130
AlmaIFIntegrator::integrateCore
virtual bool integrateCore(const ProGe::NetlistBlock &cores, int coreId)
Definition: AlmaIFIntegrator.cc:892
AlmaIFIntegrator::almaifBlock_
ProGe::NetlistBlock * almaifBlock_
Definition: AlmaIFIntegrator.hh:133
TTAMachine::Machine::Navigator::item
ComponentType * item(int index) const
TTAMachine::FunctionUnit::operation
virtual HWOperation * operation(const std::string &name) const
Definition: FunctionUnit.cc:363
AlmaIFIntegrator::projectFileGenerator
virtual ProjectFileGenerator * projectFileGenerator() const
Definition: AlmaIFIntegrator.cc:1152
AlmaIFIntegrator::pmemHandled_
bool pmemHandled_
Definition: AlmaIFIntegrator.hh:143
PlatformIntegrator::outputFilePath
TCEString outputFilePath(TCEString fileName, bool absolute=false) const
Definition: PlatformIntegrator.cc:154
HDLTemplateInstantiator::instantiateTemplateFile
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
Definition: HDLTemplateInstantiator.cc:113
DS
#define DS
Definition: LLVMBackend.cc:124
MemInfo::portAddrw
int portAddrw
Definition: MemoryGenerator.hh:71
PlatformIntegrator::errorStream
std::ostream & errorStream() const
Definition: PlatformIntegrator.cc:278
PlatformIntegrator::addProGeFiles
void addProGeFiles() const
Definition: PlatformIntegrator.cc:640
MathTools::requiredBits0Bit0
static int requiredBits0Bit0(long unsigned int number)
TTAMachine::Machine::Navigator
Definition: Machine.hh:186
AlmaIFIntegrator::fileGen_
DefaultProjectFileGenerator * fileGen_
Definition: AlmaIFIntegrator.hh:138
ProGe::NetlistBlock::port
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
Definition: NetlistBlock.cc:97
AlmaIFIntegrator::secondPmemName_
std::string secondPmemName_
Definition: AlmaIFIntegrator.hh:147
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
Environment::dataDirPath
static std::string dataDirPath(const std::string &prog)
Definition: Environment.cc:176
MemInfo::lsuName
TCEString lsuName
Definition: MemoryGenerator.hh:75
AlmaIFIntegrator::DMEM_NAME
static const TCEString DMEM_NAME
Definition: AlmaIFIntegrator.hh:120
MemoryGenerator
Definition: MemoryGenerator.hh:85
AlmaIFIntegrator::secondDmem_
bool secondDmem_
Definition: AlmaIFIntegrator.hh:142
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