#include <AlteraHibiDpRamGenerator.hh>

Inheritance diagram for AlteraHibiDpRamGenerator:

Collaboration diagram for AlteraHibiDpRamGenerator:

Public Member Functions
	AlteraHibiDpRamGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~AlteraHibiDpRamGenerator ()

virtual bool	generatesComponentHdlFile () const

virtual std::vector< TCEString >	generateComponentFile (TCEString outputPath)

Public Member Functions inherited from AlteraMemGenerator
	AlteraMemGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~AlteraMemGenerator ()

virtual void	addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

Public Member Functions inherited from MemoryGenerator
	MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~MemoryGenerator ()

virtual bool	isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const

int	memoryTotalWidth () const

int	memoryMauSize () const

int	memoryWidthInMaus () const

int	memoryAddrWidth () const

TCEString	initializationFile () const

void	addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Member Functions
virtual bool	checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const

virtual void	connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)

virtual TCEString	moduleName () const

virtual TCEString	instanceName (int coreId, int memIndex) const

Protected Member Functions inherited from AlteraMemGenerator
std::vector< TCEString >	instantiateAlteraTemplate (const TCEString &templateFile, const TCEString &outputPath) const

virtual void	addGenerics (ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)

Protected Member Functions inherited from MemoryGenerator
virtual MemoryGenerator::BlockPair	createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

const PlatformIntegrator *	platformIntegrator () const

std::ostream &	warningStream ()

std::ostream &	errorStream ()

int	portCount () const

const HDLPort *	port (int index) const

const HDLPort *	portByKeyName (TCEString name) const

TCEString	portKeyName (const HDLPort *port) const

void	addPort (const TCEString &name, HDLPort *port)

int	parameterCount () const

const ProGe::Parameter &	parameter (int index) const

void	addParameter (const ProGe::Parameter &add)

TCEString	ttaCoreName () const

TCEString	memoryIndexString (int coreId, int memIndex) const

TCEString	templatePath () const

void	instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const

bool	hasLSUArchitecture () const

const TTAMachine::FunctionUnit &	lsuArchitecture () const

TCEString	corePortName (const TCEString &portBaseName, int coreId) const

Static Private Attributes
static const TCEString	COMPONENT_FILE

Additional Inherited Members
Protected Types inherited from MemoryGenerator
typedef std::multimap< TCEString, HDLPort * >	PortMap

typedef std::pair< ProGe::NetlistBlock , ProGe::VirtualNetlistBlock >	BlockPair

Static Protected Attributes inherited from AlteraMemGenerator
static const TCEString	INIT_FILE_G = "init_file_g"

static const TCEString	DEV_FAMILY_G = "dev_family_g"

static const TCEString	ADDRW_G = "addrw_g"

static const TCEString	DATAW_G = "dataw_g"

Detailed Description

Definition at line 43 of file AlteraHibiDpRamGenerator.hh.

Constructor & Destructor Documentation

◆ AlteraHibiDpRamGenerator()

AlteraHibiDpRamGenerator::AlteraHibiDpRamGenerator	(	int	memMauWidth,
		int	widthInMaus,
		int	addrWidth,
		TCEString	initFile,
		const PlatformIntegrator *	integrator,
		std::ostream &	warningStream,
		std::ostream &	errorStream
	)

Definition at line 52 of file AlteraHibiDpRamGenerator.cc.

                             :
     AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
                        integrator, warningStream, errorStream) {
  
     bool noInvert = false;
     TCEString byteEnableWidth;
     byteEnableWidth << DATAW_G << "/8";
     // memory port 1
     addPort("dmem1_data_in",
         new HDLPort("q_a", DATAW_G, ProGe::BIT_VECTOR, ProGe::OUT, noInvert,
             memoryTotalWidth()));
     addPort("dmem1_data_out",
         new HDLPort("data_a", DATAW_G, ProGe::BIT_VECTOR, ProGe::IN,
             noInvert, memoryTotalWidth()));
     addPort("dmem1_addr",
         new HDLPort("address_a", ADDRW_G, ProGe::BIT_VECTOR, ProGe::IN,
             noInvert, memoryAddrWidth()));
     addPort("dmem1_mem_en",
         new HDLPort("enable_a", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
     addPort("dmem1_wr_en",
         new HDLPort("wren_a", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
     addPort("dmem1_wr_mask",
         new HDLPort("byteena_a", byteEnableWidth, ProGe::BIT_VECTOR,
             ProGe::IN, noInvert, memoryWidthInMaus()));
     addPort("clk",
         new HDLPort("clock_a", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
  
     // memory port 2
     addPort("dmem2_data_in",
         new HDLPort("q_b", DATAW_G, ProGe::BIT_VECTOR, ProGe::OUT, noInvert,
             memoryTotalWidth()));
     addPort("dmem2_data_out",
         new HDLPort("data_b",DATAW_G, ProGe::BIT_VECTOR, ProGe::IN,
             noInvert, memoryTotalWidth()));
     addPort("dmem2_addr",
         new HDLPort("address_b", ADDRW_G, ProGe::BIT_VECTOR, ProGe::IN,
             noInvert, memoryAddrWidth()));
     addPort("dmem2_mem_en",
         new HDLPort("enable_b", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
     addPort("dmem2_wr_en",
         new HDLPort("wren_b", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
     addPort("dmem2_wr_mask",
         new HDLPort("byteena_b", byteEnableWidth, ProGe::BIT_VECTOR,
             ProGe::IN, noInvert, memoryWidthInMaus()));
     addPort("clk",
         new HDLPort("clock_b", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
 }

References MemoryGenerator::addPort(), AlteraMemGenerator::ADDRW_G, ProGe::BIT, ProGe::BIT_VECTOR, AlteraMemGenerator::DATAW_G, ProGe::IN, MemoryGenerator::memoryAddrWidth(), MemoryGenerator::memoryTotalWidth(), MemoryGenerator::memoryWidthInMaus(), and ProGe::OUT.

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◆ ~AlteraHibiDpRamGenerator()

AlteraHibiDpRamGenerator::~AlteraHibiDpRamGenerator ( )

virtual

Definition at line 108 of file AlteraHibiDpRamGenerator.cc.

108 {

109 }

Member Function Documentation

◆ checkFuPort()

bool AlteraHibiDpRamGenerator::checkFuPort	(	const std::string	fuPort,
		std::vector< TCEString > &	reasons
	)		const

protectedvirtual

Reimplemented from MemoryGenerator.

Definition at line 113 of file AlteraHibiDpRamGenerator.cc.

                                          {
  
     // skip the hibi ports
     TCEString hibiSignal = "hibi_";
     if (fuPort.find(hibiSignal) != TCEString::npos) {
         return true;
     }
     return MemoryGenerator::checkFuPort(fuPort, reasons);
 }

References MemoryGenerator::checkFuPort().

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◆ connectPorts()

void AlteraHibiDpRamGenerator::connectPorts	(	ProGe::NetlistBlock &	netlistBlock,
		const ProGe::NetlistPort &	memPort,
		const ProGe::NetlistPort &	corePort,
		bool	inverted,
		int	coreId
	)

protectedvirtual

Reimplemented from MemoryGenerator.

Definition at line 127 of file AlteraHibiDpRamGenerator.cc.

                 {
     
     // address ports need special connection
     if (memPort.name().find("address_") != TCEString::npos) {
         netlistBlock.netlist().connect(
             memPort, corePort, 0, 0, memoryAddrWidth());
     } else {
         MemoryGenerator::connectPorts(
             netlistBlock, memPort, corePort, inverted, coreId);
     }
 }

References ProGe::Netlist::connect(), MemoryGenerator::connectPorts(), MemoryGenerator::memoryAddrWidth(), ProGe::NetlistPort::name(), and ProGe::NetlistBlock::netlist().

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◆ generateComponentFile()

std::vector< TCEString > AlteraHibiDpRamGenerator::generateComponentFile ( TCEString outputPath )

virtual

Implements MemoryGenerator.

Definition at line 151 of file AlteraHibiDpRamGenerator.cc.

                                                                     {
  
     return instantiateAlteraTemplate(COMPONENT_FILE, outputPath);
 }

References COMPONENT_FILE, and AlteraMemGenerator::instantiateAlteraTemplate().

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◆ generatesComponentHdlFile()

bool AlteraHibiDpRamGenerator::generatesComponentHdlFile ( ) const

virtual

Implements MemoryGenerator.

Definition at line 145 of file AlteraHibiDpRamGenerator.cc.

                                                           {
     return true;
 }

◆ instanceName()

TCEString AlteraHibiDpRamGenerator::instanceName	(	int	coreId,
		int	memIndex
	)		const

protectedvirtual

Implements MemoryGenerator.

Definition at line 165 of file AlteraHibiDpRamGenerator.cc.

                                                                      {
  
     TCEString iname("onchip_dp_dmem_");
     return iname << memoryIndexString(coreId, memIndex);
 }

References MemoryGenerator::memoryIndexString().

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◆ moduleName()

TCEString AlteraHibiDpRamGenerator::moduleName ( ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 158 of file AlteraHibiDpRamGenerator.cc.

                                            {
  
     return ttaCoreName() + "_altera_onchip_dp_ram_comp";
 }

References MemoryGenerator::ttaCoreName().

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Member Data Documentation

◆ COMPONENT_FILE

const TCEString AlteraHibiDpRamGenerator::COMPONENT_FILE

staticprivate

Initial value:

=

"altera_onchip_dp_ram_comp.vhd"

Definition at line 81 of file AlteraHibiDpRamGenerator.hh.

Referenced by generateComponentFile().

The documentation for this class was generated from the following files:

Public Member Functions

Protected Member Functions

Static Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ AlteraHibiDpRamGenerator()

◆ ~AlteraHibiDpRamGenerator()

Member Function Documentation

◆ checkFuPort()

◆ connectPorts()

◆ generateComponentFile()

◆ generatesComponentHdlFile()

◆ instanceName()

◆ moduleName()

Member Data Documentation

◆ COMPONENT_FILE