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OpenASIP
2.0
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This is the complete list of members for DefaultDecoderGenerator, including all inherited members.
| addGlockPortToDecoder() | DefaultDecoderGenerator | private |
| addLockReqPortToDecoder() | DefaultDecoderGenerator | private |
| bem_ | DefaultDecoderGenerator | private |
| busCntrlSignalPinOfSocket(const TTAMachine::Socket &socket, const TTAMachine::Bus &bus) const | DefaultDecoderGenerator | private |
| busControlWidth(const TTAMachine::Socket &socket) | DefaultDecoderGenerator | privatestatic |
| busMuxCntrlRegister(const TTAMachine::Bus &bus) | DefaultDecoderGenerator | privatestatic |
| busMuxCntrlSignal(const TTAMachine::Bus &bus) | DefaultDecoderGenerator | privatestatic |
| busMuxEnableRegister(const TTAMachine::Bus &bus) | DefaultDecoderGenerator | privatestatic |
| busMuxEnableSignal(const TTAMachine::Bus &bus) | DefaultDecoderGenerator | privatestatic |
| BusSet typedef | DefaultDecoderGenerator | private |
| completeDecoderBlock(const ProGe::NetlistGenerator &nlGenerator, ProGe::NetlistBlock &coreBlock) | DefaultDecoderGenerator | |
| connectedBuses(const TTAMachine::Socket &socket) | DefaultDecoderGenerator | privatestatic |
| containsSimilarGuard(const std::set< TTAMachine::PortGuard * > &guardSet, const TTAMachine::PortGuard &guard) | DefaultDecoderGenerator | privatestatic |
| containsSimilarGuard(const std::set< TTAMachine::RegisterGuard * > &guardSet, const TTAMachine::RegisterGuard &guard) | DefaultDecoderGenerator | privatestatic |
| dataControlWidth(const TTAMachine::Socket &socket) | DefaultDecoderGenerator | privatestatic |
| decoderBlock_ | DefaultDecoderGenerator | private |
| DefaultDecoderGenerator(const TTAMachine::Machine &machine, const BinaryEncoding &bem, const CentralizedControlICGenerator &icGenerator) | DefaultDecoderGenerator | |
| dstFieldSignal(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| entityNameStr_ | DefaultDecoderGenerator | private |
| findGuard(const GPRGuardEncoding &encoding) const | DefaultDecoderGenerator | private |
| findGuard(const FUGuardEncoding &encoding) const | DefaultDecoderGenerator | private |
| fuLoadCntrlPort(const std::string &fuName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| fuLoadSignalName(const std::string &fuName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| fuOpcodeCntrlPort(const std::string &fu) | DefaultDecoderGenerator | privatestatic |
| fuOpcodeSignalName(const std::string &fu) | DefaultDecoderGenerator | privatestatic |
| gcuDataPort(const std::string &nameInADF) | DefaultDecoderGenerator | privatestatic |
| generateAlternateGlockReqHandling_ | DefaultDecoderGenerator | private |
| generateBusEnable_ | DefaultDecoderGenerator | private |
| generateDebugger_ | DefaultDecoderGenerator | private |
| generateInstructionDecoder(const ProGe::NetlistGenerator &nlGenerator, const std::string &dstDirectory) | DefaultDecoderGenerator | |
| generateLockTrace_ | DefaultDecoderGenerator | private |
| GLOCK_PORT_NAME | DefaultDecoderGenerator | static |
| GlockBitType typedef | DefaultDecoderGenerator | private |
| glockPortWidth() const | DefaultDecoderGenerator | |
| GlockReqBitType typedef | DefaultDecoderGenerator | private |
| glockRequestWidth() const | DefaultDecoderGenerator | |
| guardFieldSignal(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| guardPortName(const TTAMachine::Guard &guard) | DefaultDecoderGenerator | privatestatic |
| icGenerator_ | DefaultDecoderGenerator | private |
| immSlotSignal(const std::string &immSlot) | DefaultDecoderGenerator | privatestatic |
| indentation(unsigned int level) | DefaultDecoderGenerator | privatestatic |
| instructionTemplateCondition(const ProGe::HDL language, const std::string &iTempName) const | DefaultDecoderGenerator | private |
| iuReadLoadCntrlPort(const std::string &unitName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| iuReadLoadCntrlSignal(const std::string &unitName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| iuReadOpcodeCntrlPort(const std::string &unitName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| iuReadOpcodeCntrlSignal(const std::string &unitName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| iuWriteLoadCntrlPort(const std::string &unitName) | DefaultDecoderGenerator | privatestatic |
| iuWriteLoadCntrlSignal(const std::string &unitName) | DefaultDecoderGenerator | privatestatic |
| iuWriteOpcodeCntrlPort(const std::string &unitName) | DefaultDecoderGenerator | privatestatic |
| iuWriteOpcodeCntrlSignal(const std::string &unitName) | DefaultDecoderGenerator | privatestatic |
| iuWritePort(const std::string &iuName) | DefaultDecoderGenerator | privatestatic |
| iuWriteSignal(const std::string &iuName) | DefaultDecoderGenerator | privatestatic |
| language_ | DefaultDecoderGenerator | private |
| lockTraceStartingCycle_ | DefaultDecoderGenerator | private |
| machine_ | DefaultDecoderGenerator | private |
| moveFieldSignal(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| needsBusControl(const TTAMachine::Socket &socket) | DefaultDecoderGenerator | privatestatic |
| needsDataControl(const TTAMachine::Socket &socket) | DefaultDecoderGenerator | privatestatic |
| nlGenerator_ | DefaultDecoderGenerator | private |
| opcode(const TTAMachine::HWOperation &operation) const | DefaultDecoderGenerator | private |
| opcodeWidth(const TTAMachine::FunctionUnit &fu) const | DefaultDecoderGenerator | private |
| portCodeCondition(const ProGe::HDL language, const SocketEncoding &socketEnc, const PortCode &code) | DefaultDecoderGenerator | privatestatic |
| registerBits | DefaultDecoderGenerator | private |
| registerVectors | DefaultDecoderGenerator | private |
| requiredRFLatencies(const TTAMachine::ImmediateUnit &iu) const | DefaultDecoderGenerator | |
| rfLoadCntrlPort(const std::string &rfName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| rfLoadSignalName(const std::string &rfName, const std::string &portName, bool async=false) | DefaultDecoderGenerator | privatestatic |
| rfOpcodeCntrlPort(const std::string &rfName, const std::string &portName) | DefaultDecoderGenerator | privatestatic |
| rfOpcodeFromSrcOrDstField(const ProGe::HDL language, const SocketEncoding &socketEnc, const PortCode &code) | DefaultDecoderGenerator | privatestatic |
| rfOpcodeSignalName(const std::string &rfName, const std::string &portName, bool async=false) | DefaultDecoderGenerator | privatestatic |
| rfOpcodeWidth(const TTAMachine::BaseRegisterFile &rf) | DefaultDecoderGenerator | privatestatic |
| RISCV_SIMM_PORT_IN_NAME | DefaultDecoderGenerator | static |
| sacEnabled(const std::string &rfName) const | DefaultDecoderGenerator | private |
| setGenerateBusEnable(bool value) | DefaultDecoderGenerator | |
| setGenerateDebugger(bool generate) | DefaultDecoderGenerator | |
| setGenerateLockTrace(bool generate) | DefaultDecoderGenerator | |
| setGenerateNoLoopbackGlock(bool generate) | DefaultDecoderGenerator | |
| SetHDL(ProGe::HDL language) | DefaultDecoderGenerator | |
| setLockTraceStartingCycle(unsigned int startCycle) | DefaultDecoderGenerator | |
| setSyncReset(bool value) | DefaultDecoderGenerator | |
| simmCntrlSignalName(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| simmControlPort(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| simmDataPort(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| simmDataSignalName(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| simmPortWidth(const TTAMachine::Bus &bus) | DefaultDecoderGenerator | privatestatic |
| socketBusCntrlSignalName(const std::string &name) | DefaultDecoderGenerator | privatestatic |
| socketBusControlPort(const std::string &name) | DefaultDecoderGenerator | privatestatic |
| socketDataCntrlSignalName(const std::string &name) | DefaultDecoderGenerator | privatestatic |
| socketDataControlPort(const std::string &name) | DefaultDecoderGenerator | privatestatic |
| socketEncodingCondition(const ProGe::HDL language, const SlotField &srcField, const std::string &socketName) | DefaultDecoderGenerator | privatestatic |
| squashSignal(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| srcFieldSignal(const std::string &busName) | DefaultDecoderGenerator | privatestatic |
| syncReset_ | DefaultDecoderGenerator | private |
| unitGlockBitMap_ | DefaultDecoderGenerator | private |
| UnitGlockBitMapType typedef | DefaultDecoderGenerator | private |
| unitGlockReqBitMap_ | DefaultDecoderGenerator | private |
| UnitGlockReqBitMapType typedef | DefaultDecoderGenerator | private |
| verifyCompatibility() const | DefaultDecoderGenerator | |
| writeBusControlRulesOfOutputSocket(const TTAMachine::Socket &socket, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeBusControlRulesOfSImmSocketOfBus(const TTAMachine::Bus &bus, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeBusMuxControlLogic(const TTAMachine::Bus &bus, const std::set< TTAMachine::Socket * > outputSockets, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeComment(std::ostream &stream, int indent, std::string comment) const | DefaultDecoderGenerator | private |
| writeControlRegisterMappings(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeControlRulesOfFUInputPort(const TTAMachine::BaseFUPort &port, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeControlRulesOfFUOutputPort(const TTAMachine::BaseFUPort &port, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeControlRulesOfRFReadPort(const TTAMachine::RFPort &port, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeControlRulesOfRFWritePort(const TTAMachine::RFPort &port, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeDismemberingAndITDecompression(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeFUCntrlSignals(std::ostream &stream) | DefaultDecoderGenerator | private |
| writeFUCntrlSignals(const TTAMachine::FunctionUnit &fu, std::ostream &stream) | DefaultDecoderGenerator | private |
| writeFullNOPConstant(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeGlockHandlingSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeGlockMapping(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeImmediateSlotSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeInstructionDecoder(std::ostream &stream) | DefaultDecoderGenerator | private |
| writeInstructionDecoding(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeInstructionDismembering(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeInstructionTemplateProcedures(const ProGe::HDL language, const TTAMachine::InstructionTemplate &iTemp, int indLevel, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeLockDumpCode(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeLongImmediateTagSignal(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeLongImmediateWriteProcess(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeMainDecodingProcess(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeMoveFieldSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeNOPEncodingVHDL() const | DefaultDecoderGenerator | private |
| writePipelineFillProcess(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writePipelineFillSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeResettingOfControlRegisters(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeRFCntrlSignals(std::ostream &stream) | DefaultDecoderGenerator | private |
| writeRFSRAMDecodingProcess(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeRulesForDestinationControlSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeRulesForSourceControlSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeSignalDeclaration(std::ostream &stream, ProGe::DataType type, std::string sigName, int width) const | DefaultDecoderGenerator | private |
| writeSimmDataSignal(const TTAMachine::Bus &bus, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeSocketCntrlSignals(std::ostream &stream) | DefaultDecoderGenerator | private |
| writeSquashSignalGenerationProcess(const TTAMachine::Bus &bus, std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeSquashSignalGenerationProcesses(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeSquashSignals(std::ostream &stream) const | DefaultDecoderGenerator | private |
| writeSquashSignalSubstitution(const ProGe::HDL language, const TTAMachine::Bus &bus, const GuardEncoding &enc, const TTAMachine::Guard &guard, std::ostream &stream, int indLevel) | DefaultDecoderGenerator | privatestatic |
| ~DefaultDecoderGenerator() | DefaultDecoderGenerator | virtual |
1.8.17