OpenASIP  2.0
Public Member Functions | Private Member Functions | Static Private Member Functions | Private Attributes | List of all members
DefaultICDecoderGenerator Class Reference
Inheritance diagram for DefaultICDecoderGenerator:
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Collaboration diagram for DefaultICDecoderGenerator:
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Public Member Functions

 DefaultICDecoderGenerator (const TTAMachine::Machine &machine, const BinaryEncoding &bem)
 
virtual ~DefaultICDecoderGenerator ()
 
virtual void completeNetlist (NetlistBlock &netlistBlock, const NetlistGenerator &generator)
 
void addRV32MicroCode (NetlistBlock &netlistBlock, const NetlistGenerator &generator)
 
void generateDebuggerCode (const NetlistGenerator &generator)
 
void addDummyIfetchDebugPorts (const NetlistGenerator &generator)
 
virtual void generate (HDL language, const std::string &dstDirectory, const NetlistGenerator &generator, const IDF::MachineImplementation &implementation, const std::string &entityString)
 
virtual std::set< int > requiredRFLatencies (const TTAMachine::ImmediateUnit &iu) const
 
virtual void verifyCompatibility () const
 
- Public Member Functions inherited from ProGe::ICDecoderGeneratorPlugin
 ICDecoderGeneratorPlugin (const TTAMachine::Machine &machine, const BinaryEncoding &bem, const std::string &description)
 
virtual ~ICDecoderGeneratorPlugin ()
 
std::string pluginDescription () const
 
int recognizedParameterCount () const
 
std::string recognizedParameter (int index) const
 
std::string parameterDescription (const std::string &paramName) const
 
void setParameter (const std::string &name, const std::string &value)
 
const TTAMachine::Machine & machine () const
 
const BinaryEncoding & bem () const
 

Private Member Functions

virtual void writeGlobalDefinitions (HDL language, std::ostream &pkgStream) const
 
bool generateDebugger (bool minimal=true) const
 
bool generateBusTrace () const
 
bool hasSynchronousReset () const
 
bool generateLockTrace () const
 
bool bypassInstructionRegister () const
 
int busTraceStartingCycle () const
 
int lockTraceStartingCycle () const
 
bool generateNoSelfLockingFUs () const
 
void addInstructioRegisterBypass (HDL language, const NetlistGenerator &generator)
 
int calculateSupportedDelaySlots () const
 
void readParameters ()
 

Static Private Member Functions

static std::string vhdlDirection (ProGe::Direction direction)
 
static int dataPortWidth (const TTAMachine::Socket &socket)
 

Private Attributes

NetlistBlock * dbsmBlock
 
DefaultICGenerator * icGenerator_
 
DefaultDecoderGenerator * decoderGenerator_
 
const TTAMachine::Machine & ttamachine_
 
const BinaryEncoding & bem_
 

Additional Inherited Members

- Protected Member Functions inherited from ProGe::ICDecoderGeneratorPlugin
void addParameter (const std::string &name, const std::string &description)
 
bool hasParameterSet (const std::string &name) const
 
std::string parameterValue (const std::string &name) const
 
- Static Protected Member Functions inherited from ProGe::ICDecoderGeneratorPlugin
static TTAMachine::Socket::Direction convertDirection (HDB::Direction direction)
 

Detailed Description

Default implementation for IC/decoder generator.

Definition at line 929 of file DefaultICDecoderPlugin.cc.

Constructor & Destructor Documentation

◆ DefaultICDecoderGenerator()

DefaultICDecoderGenerator::DefaultICDecoderGenerator ( const TTAMachine::Machine &  machine,
const BinaryEncoding &  bem 
)
inline

Definition at line 931 of file DefaultICDecoderPlugin.cc.

933  : ICDecoderGeneratorPlugin(machine, bem, PLUGIN_DESCRIPTION),
934  dbsmBlock(NULL),
935  icGenerator_(NULL),
936  decoderGenerator_(NULL),
937  ttamachine_(machine),
938  bem_(bem) {
939  addParameter(
940  GENERATE_DEBUGGER_PARAM,
941  "Generates wires to the internal hardware debugger if "
942  "the value is '" + GENERATE_DEBUGGER_PARAM_INTERNAL
943  + "', and to the external debugger if the value is '"
944  + GENERATE_DEBUGGER_PARAM_EXTERNAL + "'. A minimal set of wires, "
945  "for softreset and break, are added if the value is '"
946  + GENERATE_DEBUGGER_PARAM_MINIMAL + "'.");
947  addParameter(
948  GENERATE_BUS_TRACE_PARAM,
949  "Generates code that prints bus trace if the value is '" +
950  ENABLE_FEATURE + "'.");
951  addParameter(
952  BUS_TRACE_STARTING_CYCLE,
953  "The first cycle for which the bus trace is printed.");
954  addParameter(
955  GENERATE_LOCK_TRACE_PARAM,
956  "Generates code that prints global lock trace if the value is"
957  " '" +
958  ENABLE_FEATURE + "'.");
959  addParameter(
960  LOCK_TRACE_STARTING_CYCLE,
961  "The first cycle for which the global lock trace is printed. "
962  "If value is \"" + BUS_TRACE_STARTING_CYCLE + "\" then the "
963  "value is inherited from " + BUS_TRACE_STARTING_CYCLE + ".");
964  addParameter(
965  BYPASS_FETCHBLOCK_REG_PARAM,
966  "-1 delay slot by removing instruction fetch register. "
967  "'" +
968  ENABLE_FEATURE + "' to enable the feature.");
969 
970  icGenerator_ = new DefaultICGenerator(machine);
971  decoderGenerator_ = new DefaultDecoderGenerator(
972  machine, bem, *icGenerator_);
973  }

References BUS_TRACE_STARTING_CYCLE, BYPASS_FETCHBLOCK_REG_PARAM, ENABLE_FEATURE, GENERATE_BUS_TRACE_PARAM, GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_EXTERNAL, GENERATE_DEBUGGER_PARAM_INTERNAL, GENERATE_DEBUGGER_PARAM_MINIMAL, GENERATE_LOCK_TRACE_PARAM, LOCK_TRACE_STARTING_CYCLE, and machine.

◆ ~DefaultICDecoderGenerator()

virtual DefaultICDecoderGenerator::~DefaultICDecoderGenerator ( )
inlinevirtual

Definition at line 975 of file DefaultICDecoderPlugin.cc.

975  {
976  delete icGenerator_;
977  delete decoderGenerator_;
978  }

Member Function Documentation

◆ addDummyIfetchDebugPorts()

void DefaultICDecoderGenerator::addDummyIfetchDebugPorts ( const NetlistGenerator &  generator)
inline

Definition at line 1370 of file DefaultICDecoderPlugin.cc.

1370  {
1371  NetlistBlock* fetchBlock = &generator.instructionFetch();
1372  // Connect ifetch debug ports
1373  NetlistPort* ifetchDebugLockRqPort = new NetlistPort(
1374  "db_lockreq", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
1375  ifetchDebugLockRqPort->setToStatic(ProGe::StaticSignal::GND);
1376  NetlistPort* ifetchDebugResetPort = new NetlistPort(
1377  "db_rstx", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
1378  ifetchDebugResetPort->setToStatic(ProGe::StaticSignal::VCC);
1379  new NetlistPort(
1380  "db_pc", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
1381  *fetchBlock);
1382  new NetlistPort(
1383  "db_pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
1384  *fetchBlock);
1385  new NetlistPort(
1386  "db_cyclecnt", "32", 32, ProGe::BIT_VECTOR, ProGe::OUT,
1387  *fetchBlock);
1388  new NetlistPort(
1389  "db_lockcnt", "32", 32, ProGe::BIT_VECTOR, ProGe::OUT,
1390  *fetchBlock);
1391  }

References ProGe::BIT, ProGe::BIT_VECTOR, ProGe::StaticSignal::GND, ProGe::IN, ProGe::NetlistGenerator::instructionFetch(), ProGe::OUT, ProGe::NetlistPort::setToStatic(), and ProGe::StaticSignal::VCC.

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◆ addInstructioRegisterBypass()

void DefaultICDecoderGenerator::addInstructioRegisterBypass ( HDL  language,
const NetlistGenerator &  generator 
)
inlineprivate

Enables instruction register bypass feature in the instruction fetch block.

Definition at line 1822 of file DefaultICDecoderPlugin.cc.

1823  {
1824  assert(
1825  ttamachine_.isRISCVMachine() &&
1826  "Instruction register by pass only implemented for RISC-V");
1827 
1828  // Todo: remove when this feature is added to debugger-fetch.
1829  assert(
1830  !generateDebugger() &&
1831  "addInstructionRegisterBypass(): "
1832  "debugger does not support Instruction Register Bypass "
1833  "feature yet.");
1834 
1835  NetlistBlock* ifetchBlock = &generator.instructionFetch();
1836 
1837  if (language == ProGe::VHDL) {
1838  ifetchBlock->setParameter(
1839  "bypass_fetchblock_register", "boolean", "true");
1840  } else if (language == ProGe::Verilog) {
1841  // Todo
1842  assert(
1843  false &&
1844  "Verilog version of instruction register bypass "
1845  "not implemented.");
1846  } else {
1847  assert(false && "Unknown HDL choice.");
1848  }
1849  }

References assert, ProGe::NetlistGenerator::instructionFetch(), ProGe::NetlistBlock::setParameter(), ProGe::Verilog, and ProGe::VHDL.

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◆ addRV32MicroCode()

void DefaultICDecoderGenerator::addRV32MicroCode ( NetlistBlock &  netlistBlock,
const NetlistGenerator &  generator 
)
inline

Definition at line 1004 of file DefaultICDecoderPlugin.cc.

1005  {
1006  NetlistBlock& decompressor = generator.instructionDecompressor();
1007  NetlistBlock& decoder = generator.instructionDecoder();
1008  NetlistBlock& ifetch = generator.instructionFetch();
1009  Netlist& netlist = netlistBlock.netlist();
1010 
1011  // Change port width to 32 to match socket width
1012  ifetch.port("pc_in")->setWidthFormula("32");
1013 
1014  NetlistBlock* microCodeBlock = new NetlistBlock(
1015  "rv32_microcode_wrapper", "rv32_microcode_wrapper_i");
1016 
1017  // Adds the block to the netlist
1018  netlistBlock.addSubBlock(microCodeBlock);
1019 
1020  NetlistPort* decoderRISCVSimmPort = new NetlistPort(
1021  DefaultDecoderGenerator::RISCV_SIMM_PORT_IN_NAME, "32",
1022  ProGe::BIT_VECTOR, ProGe::IN, decoder);
1023 
1024  NetlistPort* clk = new NetlistPort(
1025  "clk", "1", ProGe::BIT, ProGe::IN, *microCodeBlock);
1026 
1027  NetlistPort* rst = new NetlistPort(
1028  "rstx", "1", ProGe::BIT, ProGe::IN, *microCodeBlock);
1029 
1030  NetlistPort* glock = new NetlistPort(
1031  "glock_in", "1", ProGe::BIT, ProGe::IN, *microCodeBlock);
1032 
1033  netlist.connect(
1034  *glock, *ifetch.port(DefaultDecoderGenerator::GLOCK_PORT_NAME));
1035 
1036  netlist.connect(*clk, generator.clkPort(netlistBlock));
1037 
1038  netlist.connect(*rst, generator.rstPort(netlistBlock));
1039 
1040  NetlistPort* instructionOut = new NetlistPort(
1041  "instruction_out", "INSTRUCTIONWIDTH", BIT_VECTOR, ProGe::OUT,
1042  *microCodeBlock);
1043 
1044  NetlistPort* microCodeImmOut = new NetlistPort(
1045  RISCV_SIMM_PORT_OUT_NAME, "32", BIT_VECTOR, ProGe::OUT,
1046  *microCodeBlock);
1047 
1048  NetlistPort* instructionIn = new NetlistPort(
1049  "instruction_in", "IMEMWIDTHINMAUS*IMEMMAUWIDTH", BIT_VECTOR,
1050  ProGe::IN, *microCodeBlock);
1051 
1052  netlist.connect(*microCodeImmOut, *decoderRISCVSimmPort);
1053 
1054  netlist.disconnectPorts(
1055  *ifetch.port(NetlistGenerator::FETCHBLOCK_PORT_NAME),
1056  *decompressor.port(NetlistGenerator::FETCHBLOCK_PORT_NAME));
1057 
1058  netlist.connect(
1059  *instructionOut,
1060  *decompressor.port(NetlistGenerator::FETCHBLOCK_PORT_NAME));
1061 
1062  netlist.connect(
1063  *ifetch.port(NetlistGenerator::FETCHBLOCK_PORT_NAME),
1064  *instructionIn);
1065 
1066  decompressor.port(NetlistGenerator::FETCHBLOCK_PORT_NAME)
1067  ->setWidthFormula("INSTRUCTIONWIDTH");
1068 
1069  NetlistPort* ifetchStallPortIFetch = new NetlistPort(
1070  IFETCH_STALL_PORT_NAME, "1", ProGe::BIT, ProGe::IN, ifetch);
1071 
1072  NetlistPort* ifetchStallPortMicroCode = new NetlistPort(
1073  IFETCH_STALL_PORT_NAME, "1", ProGe::BIT, ProGe::OUT,
1074  *microCodeBlock);
1075 
1076  NetlistPort* rvJumpPortMicroCode = new NetlistPort(
1077  "rv_jump", "1", ProGe::BIT, ProGe::OUT, *microCodeBlock);
1078 
1079  NetlistPort* rvAuipcPortMicroCode = new NetlistPort(
1080  "rv_auipc", "1", ProGe::BIT, ProGe::OUT, *microCodeBlock);
1081 
1082  NetlistPort* rvOffsetPortMicroCode = new NetlistPort(
1083  "rv_offset", "32", BIT_VECTOR, ProGe::OUT, *microCodeBlock);
1084 
1085  NetlistPort* rvOffsetPortIfetch =
1086  new NetlistPort("rv_offset", "32", BIT_VECTOR, ProGe::IN, ifetch);
1087 
1088  NetlistPort* rvJumpPortIfetch =
1089  new NetlistPort("rv_jump", "1", ProGe::BIT, ProGe::IN, ifetch);
1090 
1091  NetlistPort* rvAuipcPortIfetch =
1092  new NetlistPort("rv_auipc", "1", ProGe::BIT, ProGe::IN, ifetch);
1093 
1094  netlist.connect(*rvJumpPortMicroCode, *rvJumpPortIfetch);
1095  netlist.connect(*rvAuipcPortMicroCode, *rvAuipcPortIfetch);
1096  netlist.connect(*rvOffsetPortMicroCode, *rvOffsetPortIfetch);
1097 
1098  netlist.connect(*ifetchStallPortMicroCode, *ifetchStallPortIFetch);
1099  }

References ProGe::NetlistBlock::addSubBlock(), ProGe::BIT, ProGe::BIT_VECTOR, ProGe::NetlistGenerator::clkPort(), ProGe::Netlist::connect(), ProGe::Netlist::disconnectPorts(), FETCHBLOCK_PORT_NAME, DefaultDecoderGenerator::GLOCK_PORT_NAME, IFETCH_STALL_PORT_NAME, ProGe::IN, ProGe::NetlistGenerator::instructionDecoder(), ProGe::NetlistGenerator::instructionDecompressor(), ProGe::NetlistGenerator::instructionFetch(), ProGe::NetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistBlock::port(), DefaultDecoderGenerator::RISCV_SIMM_PORT_IN_NAME, RISCV_SIMM_PORT_OUT_NAME, ProGe::NetlistGenerator::rstPort(), and ProGe::NetlistPort::setWidthFormula().

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◆ busTraceStartingCycle()

int DefaultICDecoderGenerator::busTraceStartingCycle ( ) const
inlineprivate

Returns the starting cycle to be written to the bus trace given as parameter.

Returns
The starting cycle.

Definition at line 1727 of file DefaultICDecoderPlugin.cc.

1727  {
1728  if (!hasParameterSet(BUS_TRACE_STARTING_CYCLE)) {
1729  return 0;
1730  } else {
1731  string paramValue = parameterValue(BUS_TRACE_STARTING_CYCLE);
1732  try {
1733  unsigned int cycle = Conversion::toUnsignedInt(paramValue);
1734  return cycle;
1735  } catch (const Exception&) {
1736  return 0;
1737  }
1738  }
1739  }

References BUS_TRACE_STARTING_CYCLE, and Conversion::toUnsignedInt().

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◆ bypassInstructionRegister()

bool DefaultICDecoderGenerator::bypassInstructionRegister ( ) const
inlineprivate

Tells whether instruction register should be left generated (true).

Definition at line 1708 of file DefaultICDecoderPlugin.cc.

1708  {
1709  if (!hasParameterSet(BYPASS_FETCHBLOCK_REG_PARAM)) {
1710  return false;
1711  } else {
1712  string paramValue = parameterValue(BYPASS_FETCHBLOCK_REG_PARAM);
1713  if (paramValue == BYPASS_FETCHBLOCK_REG_PARAM_YES) {
1714  return true;
1715  } else {
1716  return false;
1717  }
1718  }
1719  }

References BYPASS_FETCHBLOCK_REG_PARAM, and BYPASS_FETCHBLOCK_REG_PARAM_YES.

◆ calculateSupportedDelaySlots()

int DefaultICDecoderGenerator::calculateSupportedDelaySlots ( ) const
inlineprivate

Return number of required delay slots. By default the number is three but can be reduced or increased by options.

Definition at line 1856 of file DefaultICDecoderPlugin.cc.

1856  {
1857  int delaySlots = 3;
1858  if (bypassInstructionRegister()) {
1859  delaySlots -= 1;
1860  }
1861  return delaySlots;
1862  }

◆ completeNetlist()

virtual void DefaultICDecoderGenerator::completeNetlist ( NetlistBlock &  netlistBlock,
const NetlistGenerator &  generator 
)
inlinevirtual

Completes the given netlist by adding IC block and completing the decoder block by adding the ports connected to IC. Connects also IC to all the units in the machine.

Parameters
Thenetlist to complete.
generatorThe netlist generator which generated the netlist.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 989 of file DefaultICDecoderPlugin.cc.

990  {
991  // add interconnection network to the netlist and connect it to the
992  // units
993  icGenerator_->addICToNetlist(generator, netlistBlock);
994 
995  // complete the decoder block and connect it to the IC and units
996  decoderGenerator_->completeDecoderBlock(generator, netlistBlock);
997 
998  if (ttamachine_.isRISCVMachine()) {
999  addRV32MicroCode(netlistBlock, generator);
1000  }
1001  }

◆ dataPortWidth()

static int DefaultICDecoderGenerator::dataPortWidth ( const TTAMachine::Socket &  socket)
inlinestaticprivate

Calculates the data port width of the given socket.

Parameters
socketThe socket.
Returns
The width of the data port.

Definition at line 1805 of file DefaultICDecoderPlugin.cc.

1805  {
1806  int ports = socket.portCount();
1807  int width(0);
1808  for (int i = 0; i < ports; i++) {
1809  Port* port = socket.port(i);
1810  if (port->width() > width) {
1811  width = port->width();
1812  }
1813  }
1814  return width;
1815  }

References TTAMachine::Socket::port(), TTAMachine::Socket::portCount(), and TTAMachine::Port::width().

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◆ generate()

virtual void DefaultICDecoderGenerator::generate ( HDL  language,
const std::string &  dstDirectory,
const NetlistGenerator &  generator,
const IDF::MachineImplementation &  implementation,
const std::string &  entityString 
)
inlinevirtual

Generates the interconnection network and instruction decoder to the given destination directory.

Parameters
dstDirectoryThe destination directory.
generatorThe netlist generator that generated the netlist.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1401 of file DefaultICDecoderPlugin.cc.

1405  {
1406  const string DS = FileSystem::DIRECTORY_SEPARATOR;
1407  const string templateDir = Environment::dataDirPath("ProGe");
1408 
1409  BlockSourceCopier copier(implementation, entityString, language);
1410  MachineInfo::OperationSet cuOps =
1411  MachineInfo::getOpset(*generator.context().adf().controlUnit());
1412  Path proGeDataDir(Environment::dataDirPath("ProGe"));
1413  HDLTemplateInstantiator& instantiator =
1414  copier.getTemplateInstatiator();
1415 
1416  if (ttamachine_.isRISCVMachine()) {
1417  instantiator.replacePlaceholder(
1418  "ifetch-stall-cond",
1419  " and " + IFETCH_STALL_PORT_NAME + " = '0'");
1420  instantiator.replacePlaceholder(
1421  "ifetch-stall-port-declarations",
1422  IFETCH_STALL_PORT_NAME + " : in std_logic;");
1423 
1424  ProGe::RV32MicroCodeGenerator* microCodeGen =
1425  new RV32MicroCodeGenerator(ttamachine_, bem_);
1426  microCodeGen->setBypassInstructionRegister(
1427  bypassInstructionRegister());
1428  microCodeGen->generateRTL(instantiator, dstDirectory);
1429  }
1430 
1431  if (generateBusTrace()) {
1432  icGenerator_->setGenerateBusTrace(true);
1433  icGenerator_->setBusTraceStartingCycle(busTraceStartingCycle());
1434  } else {
1435  icGenerator_->setGenerateBusTrace(false);
1436  }
1437 
1438  try {
1439  // Check for illegal combinations in fetch/decode unit options
1440 
1441  if (!generateDebugger()) {
1442  // Signal declarations as a stand-in for debug ports
1443  instantiator.replacePlaceholderFromFile(
1444  "db-signal-declarations",
1445  proGeDataDir / "no_debug_signal_declaration.snippet");
1446  }
1447 
1448  if (hasSynchronousReset()) {
1449  if (language == VHDL) {
1450  generator.instructionFetch().setParameter(
1451  "sync_reset_g", "boolean", "true");
1452  instantiator.replacePlaceholder("sync-waitlist", "clk");
1453  } else { // language == Verilog
1454  instantiator.replacePlaceholder(
1455  "update-condition", "always@(posedge clk)");
1456  }
1457  } else {
1458  if (language == VHDL) {
1459  instantiator.replacePlaceholder(
1460  "sync-waitlist", "clk, rstx");
1461  } else { // language == Verilog
1462  instantiator.replacePlaceholder(
1463  "update-condition",
1464  "always@(posedge clk or negedge rstx)");
1465  }
1466  }
1467 
1468  if (generateNoSelfLockingFUs()) {
1469  decoderGenerator_->setGenerateNoLoopbackGlock(true);
1470  if (language == VHDL) {
1471  generator.instructionFetch().setParameter(
1472  "no_glock_loopback_g", "std_logic", "'1'");
1473  } // todo verilog version
1474  }
1475 
1476  // Set the pc opcode port width
1477  std::size_t reqOpcodeWidth =
1478  CUOpcodeGenerator::gcuOpcodeWidth(ttamachine_);
1479  instantiator.replacePlaceholder(
1480  "pc-opcode-len", Conversion::toString(reqOpcodeWidth - 1));
1481 
1482  instantiator.replacePlaceholderFromFile(
1483  "default-instr-reg-write",
1484  Path(proGeDataDir / "default-instr-reg-write.snippet"));
1485 
1486  // Next PC process sensitivity list
1487  std::string sensitivityStringPCBypassed =
1488  "pc_in, pc_reg, increased_pc ";
1489  std::string sensitivityStringPCNotBypassed = "";
1490  // Complete the default sensitivity list
1491  sensitivityStringPCBypassed += ",\n pc_load, pc_opcode";
1492  instantiator.replacePlaceholder( // This is bypassed too
1493  "pc-sensitivity-list-pc-bypass", sensitivityStringPCBypassed);
1494 
1495  // Next PC signal assign condition
1496  std::string conditionString =
1497  "pc_load = '1' and ((unsigned(pc_opcode) = IFE_CALL or \n"
1498  " unsigned(pc_opcode) = IFE_JUMP))\n";
1499  instantiator.replacePlaceholder(
1500  "not-bypassed-next-pc-condition", conditionString);
1501 
1502  if (generateDebugger()) { // DEBUGTODO
1503  if (language != VHDL) {
1504  std::string errorMsg =
1505  "Language not set to VHDL when HW debugger is in "
1506  "use.";
1507  throw Exception(__FILE__, __LINE__, __func__, errorMsg);
1508  }
1509 
1510  generator.instructionFetch().setParameter(
1511  "debug_logic_g", "boolean", "true");
1512  if (parameterValue(GENERATE_DEBUGGER_PARAM) ==
1513  GENERATE_DEBUGGER_PARAM_MINIMAL) {
1514  instantiator.replacePlaceholderFromFile(
1515  "db-port-declarations",
1516  Path(proGeDataDir/"debug_minimal_port_declaration.snippet"));
1517  instantiator.replacePlaceholderFromFile(
1518  "db-signal-declarations",
1519  Path(proGeDataDir/"debug_minimal_signal_declaration.snippet"));
1520  } else {
1521  instantiator.replacePlaceholderFromFile(
1522  "db-port-declarations",
1523  Path(proGeDataDir/"debug_port_declaration.snippet"));
1524  instantiator.replacePlaceholderFromFile(
1525  "db-signal-declarations",
1526  Path(proGeDataDir/"debug_signal_declaration.snippet"));
1527  }
1528  copier.instantiateHDLTemplate(
1529  templateDir + DS + "ifetch." +
1530  (language == VHDL ? "vhdl" : "v") + ".tmpl",
1531  dstDirectory,
1532  std::string("ifetch.") +
1533  (language == VHDL ? "vhdl" : "v"));
1534  } else {
1535  copier.instantiateHDLTemplate(
1536  templateDir + DS + "ifetch." +
1537  (language == VHDL ? "vhdl" : "v") + ".tmpl",
1538  dstDirectory,
1539  std::string("ifetch.") +
1540  (language == VHDL ? "vhdl" : "v"));
1541  }
1542  } catch (const Exception& e) {
1543  abortWithError(e.errorMessage());
1544  }
1545 
1546  if (bypassInstructionRegister()) {
1547  if (language != VHDL) {
1548  std::string errorMsg =
1549  "Instruction register bypass is not supported for "
1550  "given HDL.";
1551  throw Exception(__FILE__, __LINE__, __func__, errorMsg);
1552  }
1553 
1554  addInstructioRegisterBypass(language, generator);
1555  }
1556 
1557  // generate the IC
1558  icGenerator_->SetHDL(language);
1559  icGenerator_->generateInterconnectionNetwork(dstDirectory);
1560  // generate the decoder
1561  decoderGenerator_->SetHDL(language);
1562  decoderGenerator_->generateInstructionDecoder(generator, dstDirectory);
1563 
1564  if (generateDebugger()) {
1565  if (language != VHDL) {
1566  std::string errorMsg =
1567  "Language not set to VHDL when HW debugger is in use.";
1568  throw Exception(__FILE__, __LINE__, __func__, errorMsg);
1569  } else {
1570  generateDebuggerCode(generator);
1571  }
1572  }
1573  if (ttamachine_.isRISCVMachine()) {
1574  copier.instantiateHDLTemplate(
1575  templateDir + DS + "rv32_ifetch.vhdl.tmpl", dstDirectory,
1576  "ifetch.vhdl");
1577  } else {
1578  copier.instantiateHDLTemplate(
1579  templateDir + DS + "ifetch.vhdl.tmpl", dstDirectory,
1580  "ifetch.vhdl");
1581  }
1582  }

References __func__, abortWithError, ProGe::ProGeContext::adf(), ProGe::NetlistGenerator::context(), TTAMachine::Machine::controlUnit(), Environment::dataDirPath(), FileSystem::DIRECTORY_SEPARATOR, DS, Exception::errorMessage(), GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_MINIMAL, ProGe::RV32MicroCodeGenerator::generateRTL(), MachineInfo::getOpset(), ProGe::BlockSourceCopier::getTemplateInstatiator(), IFETCH_STALL_PORT_NAME, implementation, ProGe::BlockSourceCopier::instantiateHDLTemplate(), ProGe::NetlistGenerator::instructionFetch(), HDLTemplateInstantiator::replacePlaceholder(), HDLTemplateInstantiator::replacePlaceholderFromFile(), ProGe::RV32MicroCodeGenerator::setBypassInstructionRegister(), ProGe::NetlistBlock::setParameter(), Conversion::toString(), and ProGe::VHDL.

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◆ generateBusTrace()

bool DefaultICDecoderGenerator::generateBusTrace ( ) const
inlineprivate

Tells whether IC generator should generate bus tracing code.

Returns
True if IC generator should generate the code.

Definition at line 1667 of file DefaultICDecoderPlugin.cc.

1667  {
1668  if (!hasParameterSet(GENERATE_BUS_TRACE_PARAM)) {
1669  return false;
1670  } else {
1671  string paramValue = parameterValue(GENERATE_BUS_TRACE_PARAM);
1672  if (paramValue == GENERATE_BUS_TRACE_PARAM_YES) {
1673  return true;
1674  } else {
1675  return false;
1676  }
1677  }
1678  }

References GENERATE_BUS_TRACE_PARAM, and GENERATE_BUS_TRACE_PARAM_YES.

◆ generateDebugger()

bool DefaultICDecoderGenerator::generateDebugger ( bool  minimal = true) const
inlineprivate

Tells whether IC generator should generate debug interface code.

Returns
True if IC generator should generate the code.

Definition at line 1646 of file DefaultICDecoderPlugin.cc.

1646  {
1647  if (!hasParameterSet(GENERATE_DEBUGGER_PARAM)) {
1648  return false;
1649  } else {
1650  string paramValue = parameterValue(GENERATE_DEBUGGER_PARAM);
1651  if (paramValue == GENERATE_DEBUGGER_PARAM_YES ||
1652  paramValue == GENERATE_DEBUGGER_PARAM_INTERNAL ||
1653  paramValue == GENERATE_DEBUGGER_PARAM_EXTERNAL ||
1654  (paramValue == GENERATE_DEBUGGER_PARAM_MINIMAL && minimal)) {
1655  return true;
1656  } else {
1657  return false;
1658  }
1659  }
1660  }

References GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_EXTERNAL, GENERATE_DEBUGGER_PARAM_INTERNAL, GENERATE_DEBUGGER_PARAM_MINIMAL, and GENERATE_DEBUGGER_PARAM_YES.

◆ generateDebuggerCode()

void DefaultICDecoderGenerator::generateDebuggerCode ( const NetlistGenerator &  generator)
inline

Definition at line 1101 of file DefaultICDecoderPlugin.cc.

1101  {
1102  assert(
1103  generateDebugger() &&
1104  "Entered debugger connection generation without cause.");
1105 
1106  NetlistBlock* decoderBlock = &generator.instructionDecoder();
1107  NetlistBlock& toplevelBlock = decoderBlock->parentBlock();
1108  std::string addrWidthFormula = generator.gcuReturnAddressInPort()
1109  .widthFormula();
1110  NetlistBlock* fetchBlock = &generator.instructionFetch();
1111  NetlistBlock* icBlock = NULL;
1112 
1113  bool is_external = false, is_internal = false, is_minimal = false;
1114 
1115  if (parameterValue(GENERATE_DEBUGGER_PARAM) ==
1116  GENERATE_DEBUGGER_PARAM_EXTERNAL) {
1117  is_external = true;
1118  } else if (parameterValue(GENERATE_DEBUGGER_PARAM) ==
1119  GENERATE_DEBUGGER_PARAM_MINIMAL) {
1120  is_minimal = true;
1121  } else {
1122  is_internal = true;
1123  }
1124 
1125  for (std::size_t i = 0; i < toplevelBlock.subBlockCount(); i++) {
1126  icBlock = &toplevelBlock.subBlock(i);
1127  if (icBlock->instanceName() == "ic")
1128  break;
1129  if (icBlock->moduleName() == "ic")
1130  break;
1131  }
1132 
1133  if (is_internal) {
1134  //Include debugger package with width constants in tta0.vhdl
1135  toplevelBlock.addPackage("debugger_if");
1136  }
1137 
1138  NetlistPort* ttaResetPort = new NetlistPort(
1139  "db_tta_nreset", "1", BIT, ProGe::IN, toplevelBlock);
1140  NetlistPort *ttaLockcountPort = new NetlistPort("db_lockcnt",
1141  "64", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1142  NetlistPort *ttaCyclecountPort = new NetlistPort("db_cyclecnt",
1143  "64", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1144 
1145  NetlistPort *ttaPCPort = new NetlistPort("db_pc",
1146  "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1147 
1148  if (is_minimal || is_external) {
1149 
1150  NetlistPort* dbGlockReqPort = new NetlistPort(
1151  "db_lockrq", "1", BIT, ProGe::IN, toplevelBlock);
1152 
1153  // Connect to the highest bit of decoder lockrq vector, others are
1154  // already connected
1155  NetlistPort* decoderGlockReqPort =
1156  decoderBlock->port("lock_req");
1157  int bit = decoderGenerator_->glockRequestWidth()-1;
1158  toplevelBlock.netlist().connect(
1159  *dbGlockReqPort, *decoderGlockReqPort, 0, bit, 1);
1160 
1161  // Connect ifetch debug ports
1162  NetlistPort* ifetchDebugResetPort = new NetlistPort(
1163  "db_rstx", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
1164  toplevelBlock.netlist().connect(*ttaResetPort,
1165  *ifetchDebugResetPort);
1166 
1167  NetlistPort* ifetchDebugLockRqPort = new NetlistPort(
1168  "db_lockreq", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
1169  toplevelBlock.netlist().connect(*dbGlockReqPort,
1170  *ifetchDebugLockRqPort);
1171 
1172  NetlistPort* ifetchCyclecountPort = new NetlistPort(
1173  "db_cyclecnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
1174  *fetchBlock);
1175  toplevelBlock.netlist().connect(
1176  *ifetchCyclecountPort, *ttaCyclecountPort);
1177  NetlistPort* ifetchLockcountPort = new NetlistPort(
1178  "db_lockcnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
1179  *fetchBlock);
1180  toplevelBlock.netlist().connect(
1181  *ifetchLockcountPort, *ttaLockcountPort);
1182 
1183  NetlistPort* ifetchPCPort = new NetlistPort(
1184  "db_pc", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
1185  *fetchBlock);
1186  toplevelBlock.netlist().connect(*ifetchPCPort, *ttaPCPort);
1187  }
1188  if (!is_minimal) {
1189  //Add debugger interface ports to tta0 entity
1190  NetlistPort *ttaPCStartPort = new NetlistPort("db_pc_start",
1191  "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::IN, toplevelBlock);
1192  NetlistPort *ttaBustracePort = new NetlistPort("db_bustraces",
1193  "BUSTRACE_WIDTH", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1194 
1195  // Connect bustraces out and away
1196  NetlistPort* icBustracePort = icBlock->port("db_bustraces");
1197  assert(icBustracePort);
1198  toplevelBlock.netlist().connect(
1199  *icBustracePort, *ttaBustracePort);
1200 
1201  if (is_external) {
1202  NetlistPort* dbPCNextPort = new NetlistPort(
1203  "db_pc_next", "IMEMADDRWIDTH",
1204  ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1205 
1206  NetlistPort* ifetchPCStartPort = new NetlistPort(
1207  "db_pc_start", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
1208  ProGe::IN, *fetchBlock);
1209  toplevelBlock.netlist().connect(*ifetchPCStartPort,
1210  *ttaPCStartPort);
1211  NetlistPort* ifetchPCNextPort = new NetlistPort(
1212  "db_pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
1213  ProGe::OUT, *fetchBlock);
1214  toplevelBlock.netlist().connect(*ifetchPCNextPort,
1215  *dbPCNextPort);
1216 
1217  } else if (is_internal) { // Generate internal debugger
1218  NetlistPort* ttaBpEnaPort = new NetlistPort(
1219  "db_bp_ena", "1+db_breakpoints",
1220  ProGe::BIT_VECTOR, ProGe::IN, toplevelBlock);
1221  NetlistPort* ttaBp0Port = new NetlistPort(
1222  "bp_target_cc", "db_breakpoints_cc*db_data_width",
1223  ProGe::BIT_VECTOR, ProGe::IN, toplevelBlock);
1224  NetlistPort* ttaBp41Port = new NetlistPort(
1225  "bp_target_pc", "db_breakpoints_pc*IMEMADDRWIDTH",
1226  ProGe::BIT_VECTOR, ProGe::IN,
1227  toplevelBlock);
1228  NetlistPort* ttaBpHitPort = new NetlistPort(
1229  "db_bp_hit", "2+db_breakpoints",
1230  ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1231  NetlistPort* ttaContinuePort = new NetlistPort(
1232  "db_tta_continue", "1", BIT, ProGe::IN, toplevelBlock);
1233  NetlistPort* ttaForceBreakPort = new NetlistPort(
1234  "db_tta_forcebreak", "1", BIT, ProGe::IN, toplevelBlock);
1235  NetlistPort* ttaStdoutBreakPort = new NetlistPort(
1236  "db_tta_stdoutbreak", "1", BIT, ProGe::IN, toplevelBlock);
1237 
1238  //Build and connect the debugger state machine block in tta0.vhdl
1239  dbsmBlock = new NetlistBlock("dbsm", "dbsm_1");
1240  toplevelBlock.addSubBlock(dbsmBlock);
1241 
1242  dbsmBlock->setParameter("cyclecnt_width_g", "integer",
1243  "db_data_width");
1244  dbsmBlock->setParameter("pc_width_g", "integer",
1245  "IMEMADDRWIDTH");
1246 
1247  NetlistPort* dbsmClkPort = new NetlistPort(
1248  "clk", "1", BIT, ProGe::IN, *dbsmBlock);
1249  toplevelBlock.netlist().connect(
1250  *dbsmClkPort, generator.clkPort(toplevelBlock));
1251 
1252  NetlistPort* dbsmNresetPort = new NetlistPort(
1253  "nreset", "1", BIT, ProGe::IN, *dbsmBlock);
1254  toplevelBlock.netlist().connect(
1255  *dbsmNresetPort, generator.rstPort(toplevelBlock));
1256 
1257  NetlistPort* dbsmBpEnaPort = new NetlistPort(
1258  "bp_ena", "1+db_breakpoints",
1259  ProGe::BIT_VECTOR, ProGe::IN, *dbsmBlock);
1260  toplevelBlock.netlist().connect(*ttaBpEnaPort, *dbsmBpEnaPort);
1261 
1262  NetlistPort* dbsmBp0Port = new NetlistPort(
1263  "bp_target_cc", "db_breakpoints_cc*cyclecnt_width_g",
1264  ProGe::BIT_VECTOR,
1265  ProGe::IN, *dbsmBlock);
1266  toplevelBlock.netlist().connect(*ttaBp0Port, *dbsmBp0Port);
1267 
1268  NetlistPort* dbsmCyclecountPort = new NetlistPort(
1269  "cyclecnt", "cyclecnt_width_g", ProGe::BIT_VECTOR,
1270  ProGe::IN, *dbsmBlock);
1271 
1272  NetlistPort* dbsmBp41Port = new NetlistPort(
1273  "bp_target_pc", "db_breakpoints_pc*IMEMADDRWIDTH",
1274  ProGe::BIT_VECTOR, ProGe::IN, *dbsmBlock);
1275  toplevelBlock.netlist().connect(*ttaBp41Port, *dbsmBp41Port);
1276 
1277  NetlistPort* dbsmPCNextPort = new NetlistPort(
1278  "pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
1279  ProGe::IN, *dbsmBlock);
1280 
1281  NetlistPort* dbsmContinuePort = new NetlistPort(
1282  "tta_continue", "1", BIT, ProGe::IN, *dbsmBlock);
1283  toplevelBlock.netlist().connect(
1284  *ttaContinuePort, *dbsmContinuePort);
1285 
1286  NetlistPort* dbsmForceBreakPort = new NetlistPort(
1287  "tta_forcebreak", "1", BIT, ProGe::IN, *dbsmBlock);
1288  toplevelBlock.netlist().connect(*ttaForceBreakPort,
1289  *dbsmForceBreakPort);
1290 
1291  NetlistPort* dbsmStdoutBreakPort = new NetlistPort(
1292  "tta_stdoutbreak", "1", BIT, ProGe::IN, *dbsmBlock);
1293  toplevelBlock.netlist().connect(
1294  *ttaStdoutBreakPort, *dbsmStdoutBreakPort);
1295 
1296  NetlistPort* dbsmBpHitPort = new NetlistPort(
1297  "bp_hit", "2+db_breakpoints",
1298  ProGe::BIT_VECTOR, ProGe::OUT, *dbsmBlock);
1299  toplevelBlock.netlist().connect(*ttaBpHitPort, *dbsmBpHitPort);
1300 
1301  NetlistPort* dbsmExtlockPort = new NetlistPort(
1302  "extlock", "1", BIT, ProGe::IN, *dbsmBlock);
1303  toplevelBlock.netlist().connect(
1304  *toplevelBlock.port("busy"), *dbsmExtlockPort);
1305 
1306 
1307  // Connect to the highest bit of decoder lockrq vector, others are
1308  // already connected
1309  NetlistPort* dbsmGlockReqPort = new NetlistPort(
1310  "bp_lockrq", "1", BIT, ProGe::OUT, *dbsmBlock);
1311  NetlistPort* decoderGlockReqPort =
1312  decoderBlock->port("lock_req");
1313  int bit = decoderGenerator_->glockRequestWidth()-1;
1314  toplevelBlock.netlist().connect(
1315  *dbsmGlockReqPort, *decoderGlockReqPort, 0, bit, 1);
1316 
1317  // Connect ifetch debug ports
1318  NetlistPort* ifetchDebugLockRqPort = new NetlistPort(
1319  "db_lockreq", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
1320  toplevelBlock.netlist().connect(*dbsmGlockReqPort,
1321  *ifetchDebugLockRqPort);
1322  NetlistPort* ifetchDebugResetPort = new NetlistPort(
1323  "db_rstx", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
1324  toplevelBlock.netlist().connect(*ttaResetPort,
1325  *ifetchDebugResetPort);
1326  NetlistPort* ifetchPCStartPort = new NetlistPort(
1327  "db_pc_start", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::IN,
1328  *fetchBlock);
1329  toplevelBlock.netlist().connect(*ifetchPCStartPort,
1330  *ttaPCStartPort);
1331  NetlistPort* ifetchPCPort = new NetlistPort(
1332  "db_pc", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
1333  *fetchBlock);
1334  toplevelBlock.netlist().connect(*ifetchPCPort, *ttaPCPort);
1335  NetlistPort* ifetchPCNextPort = new NetlistPort(
1336  "db_pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
1337  *fetchBlock);
1338  toplevelBlock.netlist().connect(
1339  *ifetchPCNextPort, *dbsmPCNextPort);
1340  NetlistPort* ifetchCyclecountPort = new NetlistPort(
1341  "db_cyclecnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
1342  *fetchBlock);
1343  toplevelBlock.netlist().connect(
1344  *ifetchCyclecountPort, *ttaCyclecountPort);
1345  toplevelBlock.netlist().connect(
1346  *ifetchCyclecountPort, *dbsmCyclecountPort);
1347  NetlistPort* ifetchLockcountPort = new NetlistPort(
1348  "db_lockcnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
1349  *fetchBlock);
1350  toplevelBlock.netlist().connect(
1351  *ifetchLockcountPort, *ttaLockcountPort);
1352  NetlistPort *ttaInstrPort = new NetlistPort(
1353  "db_instr", "IMEMWIDTHINMAUS*IMEMMAUWIDTH",
1354  ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
1355  NetlistPort* ifetchFetchblockPort =
1356  fetchBlock->port("fetchblock");
1357  toplevelBlock.netlist().connect(
1358  *ifetchFetchblockPort, *ttaInstrPort);
1359 
1360  }
1361  }
1362 
1363  // Connect decoder softreset
1364  NetlistPort* decoderDBResetPort = decoderBlock->port("db_tta_nreset");
1365  decoderDBResetPort->unsetStatic();
1366  toplevelBlock.netlist().connect(*ttaResetPort, *decoderDBResetPort);
1367  }

References ProGe::NetlistBlock::addPackage(), ProGe::NetlistBlock::addSubBlock(), assert, ProGe::BIT, ProGe::BIT_VECTOR, ProGe::NetlistGenerator::clkPort(), ProGe::Netlist::connect(), ProGe::NetlistGenerator::gcuReturnAddressInPort(), GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_EXTERNAL, GENERATE_DEBUGGER_PARAM_MINIMAL, ProGe::IN, ProGe::BaseNetlistBlock::instanceName(), ProGe::NetlistGenerator::instructionDecoder(), ProGe::NetlistGenerator::instructionFetch(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistBlock::parentBlock(), ProGe::NetlistBlock::port(), ProGe::NetlistGenerator::rstPort(), ProGe::NetlistBlock::subBlock(), ProGe::NetlistBlock::subBlockCount(), ProGe::NetlistPort::unsetStatic(), and ProGe::NetlistPort::widthFormula().

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◆ generateLockTrace()

bool DefaultICDecoderGenerator::generateLockTrace ( ) const
inlineprivate

Tells whether IC generator should generate global lock tracing code.

Returns
True if IC generator should generate the code.

Definition at line 1691 of file DefaultICDecoderPlugin.cc.

1691  {
1692  if (!hasParameterSet(GENERATE_LOCK_TRACE_PARAM)) {
1693  return false;
1694  } else {
1695  string paramValue = parameterValue(GENERATE_LOCK_TRACE_PARAM);
1696  if (paramValue == GENERATE_LOCK_TRACE_PARAM_YES) {
1697  return true;
1698  } else {
1699  return false;
1700  }
1701  }
1702  }

References GENERATE_LOCK_TRACE_PARAM, and GENERATE_LOCK_TRACE_PARAM_YES.

◆ generateNoSelfLockingFUs()

bool DefaultICDecoderGenerator::generateNoSelfLockingFUs ( ) const
inlineprivate

Definition at line 1770 of file DefaultICDecoderPlugin.cc.

1770  {
1771  if (!hasParameterSet(NO_SELF_LOCKING_PARAM)) {
1772  return false;
1773  } else {
1774  string paramValue = parameterValue(NO_SELF_LOCKING_PARAM);
1775  return paramValue == NO_SELF_LOCKING_PARAM_YES;
1776  }
1777  }

References NO_SELF_LOCKING_PARAM, and NO_SELF_LOCKING_PARAM_YES.

◆ hasSynchronousReset()

bool DefaultICDecoderGenerator::hasSynchronousReset ( ) const
inlineprivate

Definition at line 1681 of file DefaultICDecoderPlugin.cc.

1681  {
1682  return hasParameterSet(SYNC_RESET) &&
1683  parameterValue(SYNC_RESET) == ENABLE_FEATURE;
1684  }

References ENABLE_FEATURE, and SYNC_RESET.

◆ lockTraceStartingCycle()

int DefaultICDecoderGenerator::lockTraceStartingCycle ( ) const
inlineprivate

Returns the starting cycle to be written to the global lock trace given as parameter.

If parameter is not defined use value from busTraceStartingCycle() instead.

Returns
The starting cycle.

Definition at line 1750 of file DefaultICDecoderPlugin.cc.

1750  {
1751  if (!hasParameterSet(LOCK_TRACE_STARTING_CYCLE)) {
1752  return busTraceStartingCycle();
1753  } else {
1754  string paramValue = parameterValue(LOCK_TRACE_STARTING_CYCLE);
1755 
1756  if (paramValue == BUS_TRACE_STARTING_CYCLE) {
1757  return busTraceStartingCycle();
1758  }
1759 
1760  try {
1761  unsigned int cycle = Conversion::toUnsignedInt(paramValue);
1762  return cycle;
1763  } catch (const Exception&) {
1764  return 0;
1765  }
1766  }
1767  }

References BUS_TRACE_STARTING_CYCLE, LOCK_TRACE_STARTING_CYCLE, and Conversion::toUnsignedInt().

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◆ readParameters()

void DefaultICDecoderGenerator::readParameters ( )
inlineprivatevirtual

Reads parameters and configures the IC and decoder generators.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1868 of file DefaultICDecoderPlugin.cc.

1868  {
1869  icGenerator_->setExportBustrace(generateDebugger());
1870  decoderGenerator_->setGenerateDebugger(generateDebugger());
1871  // IC is combinatorial, no need for reset
1872  decoderGenerator_->setSyncReset(hasSynchronousReset());
1873 
1874  if (generateBusTrace()) {
1875  icGenerator_->setGenerateBusTrace(true);
1876  icGenerator_->setBusTraceStartingCycle(busTraceStartingCycle());
1877  } else {
1878  icGenerator_->setGenerateBusTrace(false);
1879  decoderGenerator_->setGenerateBusEnable(false);
1880  }
1881 
1882  if (generateLockTrace()) {
1883  decoderGenerator_->setGenerateLockTrace(true);
1884  decoderGenerator_->setLockTraceStartingCycle(
1885  lockTraceStartingCycle());
1886  } else {
1887  decoderGenerator_->setGenerateLockTrace(false);
1888  }
1889  }

◆ requiredRFLatencies()

virtual std::set<int> DefaultICDecoderGenerator::requiredRFLatencies ( const TTAMachine::ImmediateUnit &  iu) const
inlinevirtual

Returns the required latency of the hardware implementation of the given immediate unit.

Parameters
iuThe immediate unit.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1591 of file DefaultICDecoderPlugin.cc.

1591  {
1592  return decoderGenerator_->requiredRFLatencies(iu);
1593  }

◆ verifyCompatibility()

virtual void DefaultICDecoderGenerator::verifyCompatibility ( ) const
inlinevirtual

Verifies that the plugin is compatible with the machine.

Exceptions
InvalidDataIf the plugin is not compatible with the machine.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1602 of file DefaultICDecoderPlugin.cc.

1602  {
1603  int requiredDelaySlots = calculateSupportedDelaySlots();
1604  int specifiedDelaySlots = ttamachine_.controlUnit()->delaySlots();
1605 
1606  if (specifiedDelaySlots != requiredDelaySlots) {
1607  throw InvalidData(
1608  __FILE__, __LINE__, __func__,
1609  TCEString("Decoder generator supports ") +
1610  Conversion::toString(requiredDelaySlots + 1) +
1611  "-stage transport pipeline of GCU with given options. "
1612  "Given machine has " +
1613  Conversion::toString(specifiedDelaySlots + 1) +
1614  " stages");
1615  }
1616 
1617  icGenerator_->verifyCompatibility();
1618  decoderGenerator_->verifyCompatibility();
1619  }

References __func__, and Conversion::toString().

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◆ vhdlDirection()

static std::string DefaultICDecoderGenerator::vhdlDirection ( ProGe::Direction  direction)
inlinestaticprivate

Converts the given direction to a string.

Parameters
directionThe direction.
Returns
The direction as string in VHDL.

Definition at line 1786 of file DefaultICDecoderPlugin.cc.

1786  {
1787  switch (direction) {
1788  case ProGe::IN:
1789  return "in";
1790  case ProGe::OUT:
1791  return "out";
1792  case ProGe::BIDIR:
1793  return "inout";
1794  }
1795  assert(false);
1796  return std::string();
1797  }

References assert, ProGe::BIDIR, ProGe::IN, and ProGe::OUT.

◆ writeGlobalDefinitions()

virtual void DefaultICDecoderGenerator::writeGlobalDefinitions ( HDL  language,
std::ostream &  pkgStream 
) const
inlineprivatevirtual

Returns global package definitions in the form of a stream specifically for the variable length instruction architecture.

Parameters
pkgStreamThe destination stream

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1629 of file DefaultICDecoderPlugin.cc.

1629  {
1630  if (language == ProGe::VHDL) {
1631  pkgStream << " -- instruction width" << endl
1632  << " constant INSTRUCTIONWIDTH : positive := "
1633  << bem().width() << ";" << endl;
1634  } else if (language == ProGe::Verilog) {
1635  pkgStream << "// instruction width" << endl
1636  << "parameter INSTRUCTIONWIDTH = " << bem().width()
1637  << endl;
1638  }
1639  }

References ProGe::Verilog, and ProGe::VHDL.

Member Data Documentation

◆ bem_

const BinaryEncoding& DefaultICDecoderGenerator::bem_
private

Definition at line 1896 of file DefaultICDecoderPlugin.cc.

◆ dbsmBlock

NetlistBlock* DefaultICDecoderGenerator::dbsmBlock
private

Definition at line 1891 of file DefaultICDecoderPlugin.cc.

◆ decoderGenerator_

DefaultDecoderGenerator* DefaultICDecoderGenerator::decoderGenerator_
private

Definition at line 1894 of file DefaultICDecoderPlugin.cc.

◆ icGenerator_

DefaultICGenerator* DefaultICDecoderGenerator::icGenerator_
private

Definition at line 1893 of file DefaultICDecoderPlugin.cc.

◆ ttamachine_

const TTAMachine::Machine& DefaultICDecoderGenerator::ttamachine_
private

Definition at line 1895 of file DefaultICDecoderPlugin.cc.

The documentation for this class was generated from the following file:
ProGe::NetlistGenerator::instructionFetch
NetlistBlock & instructionFetch() const
Definition: NetlistGenerator.cc:617
DefaultDecoderGenerator::requiredRFLatencies
std::set< int > requiredRFLatencies(const TTAMachine::ImmediateUnit &iu) const
Definition: DefaultDecoderGenerator.cc:692
DefaultDecoderGenerator::setGenerateLockTrace
void setGenerateLockTrace(bool generate)
Definition: DefaultDecoderGenerator.cc:759
ProGe::StaticSignal::GND
@ GND
All port signals set to low.
Definition: NetlistPort.hh:50
ProGe::NetlistGenerator::instructionDecompressor
NetlistBlock & instructionDecompressor() const
Definition: NetlistGenerator.cc:636
DefaultICDecoderGenerator::generateDebugger
bool generateDebugger(bool minimal=true) const
Definition: DefaultICDecoderPlugin.cc:1646
DefaultDecoderGenerator::setLockTraceStartingCycle
void setLockTraceStartingCycle(unsigned int startCycle)
Definition: DefaultDecoderGenerator.cc:769
ProGe::NetlistBlock::netlist
virtual const Netlist & netlist() const
Definition: BaseNetlistBlock.cc:348
ProGe::ICDecoderGeneratorPlugin::hasParameterSet
bool hasParameterSet(const std::string &name) const
Definition: ICDecoderGeneratorPlugin.cc:176
FETCHBLOCK_PORT_NAME
const string FETCHBLOCK_PORT_NAME
Definition: NetlistGenerator.cc:106
Path
Definition: FileSystem.hh:197
NO_SELF_LOCKING_PARAM_YES
const std::string NO_SELF_LOCKING_PARAM_YES
Definition: DefaultICDecoderPlugin.cc:920
TTAMachine::Socket::port
Port * port(int index) const
Definition: Socket.cc:266
TTAMachine::Socket::portCount
int portCount() const
DefaultICDecoderGenerator::hasSynchronousReset
bool hasSynchronousReset() const
Definition: DefaultICDecoderPlugin.cc:1681
DefaultDecoderGenerator::completeDecoderBlock
void completeDecoderBlock(const ProGe::NetlistGenerator &nlGenerator, ProGe::NetlistBlock &coreBlock)
Definition: DefaultDecoderGenerator.cc:223
ProGe::NetlistBlock
Definition: NetlistBlock.hh:61
ProGe::Verilog
@ Verilog
Verilog.
Definition: ProGeTypes.hh:42
TTAMachine::Machine::isRISCVMachine
bool isRISCVMachine() const
Definition: Machine.cc:1063
HDLTemplateInstantiator
Definition: HDLTemplateInstantiator.hh:45
BUS_TRACE_STARTING_CYCLE
const std::string BUS_TRACE_STARTING_CYCLE
Definition: DefaultICDecoderPlugin.cc:916
DefaultDecoderGenerator::generateInstructionDecoder
void generateInstructionDecoder(const ProGe::NetlistGenerator &nlGenerator, const std::string &dstDirectory)
Definition: DefaultDecoderGenerator.cc:666
implementation
IDF::MachineImplementation * implementation
the implementation definition of the estimated processor
Definition: EstimatorCmdLineUI.cc:61
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
ProGe::RV32MicroCodeGenerator
Definition: RV32MicroCodeGenerator.hh:67
ProGe::ProGeContext::adf
const TTAMachine::Machine & adf() const
Definition: ProGeContext.cc:57
DefaultICDecoderGenerator::generateLockTrace
bool generateLockTrace() const
Definition: DefaultICDecoderPlugin.cc:1691
DefaultICGenerator::addICToNetlist
void addICToNetlist(const ProGe::NetlistGenerator &generator, ProGe::NetlistBlock &netlistBlock)
Definition: DefaultICGenerator.cc:114
DefaultICDecoderGenerator::generateBusTrace
bool generateBusTrace() const
Definition: DefaultICDecoderPlugin.cc:1667
ProGe::ICDecoderGeneratorPlugin::bem
const BinaryEncoding & bem() const
Definition: ICDecoderGeneratorPlugin.cc:214
ProGe::NetlistPort::widthFormula
std::string widthFormula() const
Definition: NetlistPort.cc:316
TTAMachine::Port::width
virtual int width() const =0
NO_SELF_LOCKING_PARAM
const std::string NO_SELF_LOCKING_PARAM
Definition: DefaultICDecoderPlugin.cc:919
GENERATE_DEBUGGER_PARAM_INTERNAL
const std::string GENERATE_DEBUGGER_PARAM_INTERNAL
Definition: DefaultICDecoderPlugin.cc:906
ProGe::BaseNetlistBlock::instanceName
const std::string & instanceName() const
Definition: BaseNetlistBlock.cc:135
ProGe::NetlistPort::unsetStatic
void unsetStatic() const
Definition: NetlistPort.cc:417
ProGe::NetlistBlock::setParameter
void setParameter(const std::string &name, const std::string &type, const std::string &value)
Definition: NetlistBlock.cc:89
ProGe::Netlist::disconnectPorts
void disconnectPorts(const NetlistPort &port1, const NetlistPort &port2)
Definition: Netlist.cc:135
DefaultICDecoderGenerator::lockTraceStartingCycle
int lockTraceStartingCycle() const
Definition: DefaultICDecoderPlugin.cc:1750
ProGe::NetlistPort::setToStatic
void setToStatic(StaticSignal value) const
Definition: NetlistPort.cc:410
ProGe::BIDIR
@ BIDIR
Bidirectional port.
Definition: ProGeTypes.hh:55
ProGe::ICDecoderGeneratorPlugin::addParameter
void addParameter(const std::string &name, const std::string &description)
Definition: ICDecoderGeneratorPlugin.cc:159
ProGe::NetlistBlock::parentBlock
virtual const NetlistBlock & parentBlock() const override
Definition: NetlistBlock.cc:126
ProGe::StaticSignal::VCC
@ VCC
All port signals set to high.
Definition: NetlistPort.hh:51
DefaultDecoderGenerator::verifyCompatibility
void verifyCompatibility() const
Definition: DefaultDecoderGenerator.cc:704
ProGe::Netlist
Definition: Netlist.hh:63
Conversion::toString
static std::string toString(const T &source)
HDLTemplateInstantiator::replacePlaceholderFromFile
void replacePlaceholderFromFile(const std::string &key, const Path &filePath, bool append=false)
Definition: HDLTemplateInstantiator.cc:89
ProGe::NetlistBlock::addPackage
void addPackage(const std::string &packageName)
Definition: BaseNetlistBlock.cc:687
ProGe::Netlist::connect
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
Definition: Netlist.cc:83
DefaultICDecoderGenerator::bem_
const BinaryEncoding & bem_
Definition: DefaultICDecoderPlugin.cc:1896
assert
#define assert(condition)
Definition: Application.hh:86
ProGe::NetlistGenerator::clkPort
NetlistPort & clkPort(const NetlistBlock &block) const
Definition: NetlistGenerator.cc:425
TTAMachine::Machine::controlUnit
virtual ControlUnit * controlUnit() const
Definition: Machine.cc:345
abortWithError
#define abortWithError(message)
Definition: Application.hh:72
DefaultICDecoderGenerator::busTraceStartingCycle
int busTraceStartingCycle() const
Definition: DefaultICDecoderPlugin.cc:1727
DefaultICDecoderGenerator::dbsmBlock
NetlistBlock * dbsmBlock
Definition: DefaultICDecoderPlugin.cc:1891
ProGe::VHDL
@ VHDL
VHDL.
Definition: ProGeTypes.hh:41
PLUGIN_DESCRIPTION
const std::string PLUGIN_DESCRIPTION
Definition: DefaultICDecoderPlugin.cc:917
RISCV_SIMM_PORT_OUT_NAME
const std::string RISCV_SIMM_PORT_OUT_NAME
Definition: DefaultICDecoderPlugin.cc:113
InvalidData
Definition: Exception.hh:149
GENERATE_DEBUGGER_PARAM_EXTERNAL
const std::string GENERATE_DEBUGGER_PARAM_EXTERNAL
Definition: DefaultICDecoderPlugin.cc:907
DefaultICGenerator::setGenerateBusTrace
void setGenerateBusTrace(bool generate)
Definition: DefaultICGenerator.cc:337
GENERATE_DEBUGGER_PARAM_YES
const std::string GENERATE_DEBUGGER_PARAM_YES
Definition: DefaultICDecoderPlugin.cc:905
ProGe::NetlistGenerator::context
const ProGeContext & context() const
Definition: NetlistGenerator.hh:125
ProGe::NetlistGenerator::gcuReturnAddressInPort
NetlistPort & gcuReturnAddressInPort() const
Definition: NetlistGenerator.cc:551
TTAMachine::Port
Definition: Port.hh:54
BYPASS_FETCHBLOCK_REG_PARAM
const std::string BYPASS_FETCHBLOCK_REG_PARAM
Definition: DefaultICDecoderPlugin.cc:913
BinaryEncoding::width
virtual int width(const TCEString &templateName) const
Definition: BinaryEncoding.cc:768
__func__
#define __func__
Definition: Application.hh:67
GENERATE_DEBUGGER_PARAM_MINIMAL
const std::string GENERATE_DEBUGGER_PARAM_MINIMAL
Definition: DefaultICDecoderPlugin.cc:908
ENABLE_FEATURE
const std::string ENABLE_FEATURE
Definition: DefaultICDecoderPlugin.cc:903
MachineInfo::getOpset
static OperationSet getOpset(const TTAMachine::Machine &mach)
Definition: MachineInfo.cc:65
GENERATE_BUS_TRACE_PARAM_YES
const std::string GENERATE_BUS_TRACE_PARAM_YES
Definition: DefaultICDecoderPlugin.cc:910
DefaultDecoderGenerator::GLOCK_PORT_NAME
static const std::string GLOCK_PORT_NAME
Definition: DefaultDecoderGenerator.hh:117
DefaultICGenerator
Definition: DefaultICGenerator.hh:62
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
DefaultICDecoderGenerator::ttamachine_
const TTAMachine::Machine & ttamachine_
Definition: DefaultICDecoderPlugin.cc:1895
TTAMachine::ControlUnit::delaySlots
int delaySlots() const
Exception
Definition: Exception.hh:54
DefaultICDecoderGenerator::bypassInstructionRegister
bool bypassInstructionRegister() const
Definition: DefaultICDecoderPlugin.cc:1708
GENERATE_BUS_TRACE_PARAM
const std::string GENERATE_BUS_TRACE_PARAM
Definition: DefaultICDecoderPlugin.cc:909
ProGe::NetlistGenerator::rstPort
NetlistPort & rstPort(const NetlistBlock &block) const
Definition: NetlistGenerator.cc:446
SYNC_RESET
const std::string SYNC_RESET
Definition: DefaultICDecoderPlugin.cc:921
DefaultDecoderGenerator::glockRequestWidth
int glockRequestWidth() const
Definition: DefaultDecoderGenerator.cc:585
ProGe::ICDecoderGeneratorPlugin::ICDecoderGeneratorPlugin
ICDecoderGeneratorPlugin(const TTAMachine::Machine &machine, const BinaryEncoding &bem, const std::string &description)
Definition: ICDecoderGeneratorPlugin.cc:48
Exception::errorMessage
std::string errorMessage() const
Definition: Exception.cc:123
DefaultICDecoderGenerator::generateNoSelfLockingFUs
bool generateNoSelfLockingFUs() const
Definition: DefaultICDecoderPlugin.cc:1770
FileSystem::DIRECTORY_SEPARATOR
static const std::string DIRECTORY_SEPARATOR
Definition: FileSystem.hh:189
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
ProGe::RV32MicroCodeGenerator::setBypassInstructionRegister
void setBypassInstructionRegister(const bool &value)
Definition: RV32MicroCodeGenerator.cc:1563
DefaultICDecoderGenerator::addInstructioRegisterBypass
void addInstructioRegisterBypass(HDL language, const NetlistGenerator &generator)
Definition: DefaultICDecoderPlugin.cc:1822
DefaultDecoderGenerator::SetHDL
void SetHDL(ProGe::HDL language)
Definition: DefaultDecoderGenerator.cc:177
Conversion::toUnsignedInt
static unsigned int toUnsignedInt(const T &source)
ProGe::ICDecoderGeneratorPlugin::parameterValue
std::string parameterValue(const std::string &name) const
Definition: ICDecoderGeneratorPlugin.cc:189
DefaultICDecoderGenerator::generateDebuggerCode
void generateDebuggerCode(const NetlistGenerator &generator)
Definition: DefaultICDecoderPlugin.cc:1101
DefaultICGenerator::SetHDL
void SetHDL(ProGe::HDL language)
Definition: DefaultICGenerator.cc:103
HDLTemplateInstantiator::replacePlaceholder
void replacePlaceholder(const std::string &key, const std::string &replacer, bool append=false)
Definition: HDLTemplateInstantiator.cc:62
ProGe::NetlistPort::setWidthFormula
void setWidthFormula(const std::string &newFormula)
Definition: NetlistPort.cc:324
ProGe::BlockSourceCopier
Definition: BlockSourceCopier.hh:63
MachineInfo::OperationSet
TCETools::CIStringSet OperationSet
Definition: MachineInfo.hh:60
ProGe::NetlistBlock::addSubBlock
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
Definition: BaseNetlistBlock.cc:405
DefaultDecoderGenerator::setSyncReset
void setSyncReset(bool value)
Definition: DefaultDecoderGenerator.cc:187
DefaultDecoderGenerator::setGenerateBusEnable
void setGenerateBusEnable(bool value)
Definition: DefaultDecoderGenerator.cc:192
DefaultDecoderGenerator::RISCV_SIMM_PORT_IN_NAME
static const std::string RISCV_SIMM_PORT_IN_NAME
Definition: DefaultDecoderGenerator.hh:116
DefaultICGenerator::setBusTraceStartingCycle
void setBusTraceStartingCycle(unsigned int cycle)
Definition: DefaultICGenerator.cc:348
ProGe::NetlistGenerator::instructionDecoder
NetlistBlock & instructionDecoder() const
Definition: NetlistGenerator.cc:600
TCEString
Definition: TCEString.hh:53
DefaultDecoderGenerator
Definition: DefaultDecoderGenerator.hh:86
DefaultICGenerator::verifyCompatibility
void verifyCompatibility() const
Definition: DefaultICGenerator.cc:306
DefaultDecoderGenerator::setGenerateDebugger
void setGenerateDebugger(bool generate)
Definition: DefaultDecoderGenerator.cc:182
LOCK_TRACE_STARTING_CYCLE
const std::string LOCK_TRACE_STARTING_CYCLE
Definition: DefaultICDecoderPlugin.cc:915
ProGe::NetlistPort
Definition: NetlistPort.hh:70
GENERATE_LOCK_TRACE_PARAM_YES
const std::string GENERATE_LOCK_TRACE_PARAM_YES
Definition: DefaultICDecoderPlugin.cc:912
IFETCH_STALL_PORT_NAME
const std::string IFETCH_STALL_PORT_NAME
Definition: DefaultICDecoderPlugin.cc:114
ProGe::BaseNetlistBlock::moduleName
const std::string & moduleName() const
Definition: BaseNetlistBlock.cc:140
DefaultICDecoderGenerator::addRV32MicroCode
void addRV32MicroCode(NetlistBlock &netlistBlock, const NetlistGenerator &generator)
Definition: DefaultICDecoderPlugin.cc:1004
DefaultICGenerator::generateInterconnectionNetwork
void generateInterconnectionNetwork(const std::string &dstDirectory)
Definition: DefaultICGenerator.cc:283
DS
#define DS
Definition: LLVMBackend.cc:124
DefaultICDecoderGenerator::calculateSupportedDelaySlots
int calculateSupportedDelaySlots() const
Definition: DefaultICDecoderPlugin.cc:1856
ProGe::NetlistBlock::subBlockCount
virtual size_t subBlockCount() const
Definition: BaseNetlistBlock.cc:150
ProGe::NetlistBlock::subBlock
NetlistBlock & subBlock(size_t index) override
Definition: NetlistBlock.cc:110
DefaultICGenerator::setExportBustrace
void setExportBustrace(bool export_bt)
Definition: DefaultICGenerator.cc:327
ProGe::NetlistBlock::port
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
Definition: NetlistBlock.cc:97
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
BYPASS_FETCHBLOCK_REG_PARAM_YES
const std::string BYPASS_FETCHBLOCK_REG_PARAM_YES
Definition: DefaultICDecoderPlugin.cc:914
ProGe::RV32MicroCodeGenerator::generateRTL
void generateRTL(HDLTemplateInstantiator &instantiator, const std::string &fileDst)
Definition: RV32MicroCodeGenerator.cc:1556
GENERATE_LOCK_TRACE_PARAM
const std::string GENERATE_LOCK_TRACE_PARAM
Definition: DefaultICDecoderPlugin.cc:911
Environment::dataDirPath
static std::string dataDirPath(const std::string &prog)
Definition: Environment.cc:176
GENERATE_DEBUGGER_PARAM
const std::string GENERATE_DEBUGGER_PARAM
Definition: DefaultICDecoderPlugin.cc:904
DefaultICDecoderGenerator::decoderGenerator_
DefaultDecoderGenerator * decoderGenerator_
Definition: DefaultICDecoderPlugin.cc:1894
ProGe::ICDecoderGeneratorPlugin::machine
const TTAMachine::Machine & machine() const
Definition: ICDecoderGeneratorPlugin.cc:203
DefaultICDecoderGenerator::icGenerator_
DefaultICGenerator * icGenerator_
Definition: DefaultICDecoderPlugin.cc:1893
DefaultDecoderGenerator::setGenerateNoLoopbackGlock
void setGenerateNoLoopbackGlock(bool generate)
Definition: DefaultDecoderGenerator.cc:204
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