RFTestbenchGenerator Class Reference

#include <RFTestbenchGenerator.hh>

Inheritance diagram for RFTestbenchGenerator:

Collaboration diagram for RFTestbenchGenerator:

Public Member Functions
	RFTestbenchGenerator (HDB::RFEntry *rf)
virtual	~RFTestbenchGenerator ()
virtual void	generateTestbench (std::ofstream &file)
Public Member Functions inherited from TestbenchGenerator
	TestbenchGenerator ()
virtual	~TestbenchGenerator ()

Private Member Functions
void	createMachineState ()
void	parseRfPorts ()
void	createTbInstantiation ()
void	createStimulus ()
void	createTbCode ()
void	createStimulusArrays (PortDataArray &inputData, PortDataArray &inputOpcode, PortDataArray &inputLoad, PortDataArray &outputData, PortDataArray &outputOpcode, PortDataArray &outputLoad)
void	writeDataArrays (std::ostringstream &stream, PortDataArray &array, int portWidth)
int	opcodePortWidth () const

Private Attributes
HDB::RFEntry *	rfEntry_
HDB::RFImplementation *	rfImpl_
HDB::RFArchitecture *	rfArch_
TTAMachine::RegisterFile *	machRf_
MachineState *	msm_
TTAMachine::Machine *	machine_
MemorySystem *	memSystem_
std::vector< std::string >	inputPorts_
std::vector< std::string >	inputLoadPorts_
std::vector< std::string >	inputOpcodePorts_
std::vector< std::string >	outputPorts_
std::vector< std::string >	outputLoadPorts_
std::vector< std::string >	outputOpcodePorts_

Static Private Attributes
static const std::string	RF_NAME_ = "testRF"

Additional Inherited Members
Protected Types inherited from TestbenchGenerator
typedef std::map< std::string, std::vector< uint32_t > >	PortDataArray
Protected Member Functions inherited from TestbenchGenerator
virtual void	writeStimulusArray (std::ostringstream &stream, std::vector< uint32_t > &dataArray, std::string portName, int portWidth)
void	writeTbConstants (int totalCycles, int outputIgnoreCycles)
void	writeTestbench (std::ofstream &file, HDB::HWBlockImplementation *impl)
std::ostringstream &	declarationStream ()
std::ostringstream &	bindingStream ()
std::ostringstream &	signalStream ()
std::ostringstream &	instantiationStream ()
std::ostringstream &	inputArrayStream ()
std::ostringstream &	opcodeArrayStream ()
std::ostringstream &	loadArrayStream ()
std::ostringstream &	outputArrayStream ()
std::ostringstream &	tbCodeStream ()

Detailed Description

Definition at line 51 of file RFTestbenchGenerator.hh.

Constructor & Destructor Documentation

RFTestbenchGenerator()

RFTestbenchGenerator::RFTestbenchGenerator

(

HDB::RFEntry *

rf

)

Definition at line 64 of file RFTestbenchGenerator.cc.

                                                        :
    rfEntry_(rf), rfImpl_(NULL), rfArch_(NULL), machRf_(NULL), msm_(NULL),
    inputPorts_(), inputLoadPorts_(), inputOpcodePorts_(), outputPorts_(),
    outputLoadPorts_(), outputOpcodePorts_() {
 
}

~RFTestbenchGenerator()

RFTestbenchGenerator::~RFTestbenchGenerator ( )

virtual

Definition at line 71 of file RFTestbenchGenerator.cc.

                                            {
     if (msm_) {
         delete(msm_);
     }
     if (machine_) {
         delete(machine_);
     }
     if (memSystem_) {
         delete(memSystem_);
     }
}

References machine_, memSystem_, and msm_.

Member Function Documentation

createMachineState()

void RFTestbenchGenerator::createMachineState ( )

private

Creates machine state model with the RF under test in it

Definition at line 106 of file RFTestbenchGenerator.cc.

                                         {
 
    machine_ = new TTAMachine::Machine();
    int size = 0;
    if (rfArch_->hasParameterizedSize()) {
        // set reasonable default value
        size = 16;
        rfArch_->setSize(size);
    } else {
        size = rfArch_->size();
    }
    int width = 0;
    if (rfArch_->hasParameterizedWidth()) {
        width = 32;
        rfArch_->setWidth(width);
    } else {
        width = rfArch_->width();
    }
 
    string name = RF_NAME_;
    // create simulation model of the RF
    machRf_ = new TTAMachine::RegisterFile(
        name, size, width, rfArch_->maxReads(), rfArch_->maxWrites(),
        rfArch_->guardLatency(), TTAMachine::RegisterFile::NORMAL,
        rfArch_->zeroRegister());
    machine_->addRegisterFile(*machRf_);
 
    MachineStateBuilder msmBuilder;
    
    memSystem_ = new MemorySystem(*machine_);
 
    msm_ = msmBuilder.build(*machine_, *memSystem_);
}

References TTAMachine::Machine::addRegisterFile(), MachineStateBuilder::build(), HDB::RFArchitecture::guardLatency(), HDB::RFArchitecture::hasParameterizedSize(), HDB::RFArchitecture::hasParameterizedWidth(), machine_, machRf_, HDB::RFArchitecture::maxReads(), HDB::RFArchitecture::maxWrites(), memSystem_, msm_, TTAMachine::RegisterFile::NORMAL, RF_NAME_, rfArch_, HDB::RFArchitecture::setSize(), HDB::RFArchitecture::setWidth(), HDB::RFArchitecture::size(), HDB::RFArchitecture::width(), and HDB::RFArchitecture::zeroRegister().

Referenced by generateTestbench().

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createStimulus()

void RFTestbenchGenerator::createStimulus ( )

private

Creates input and output data tables

Creates input and output data and control signals as well for the testbench. Testbench writes to and reads from every register. If RF has multiple write or read ports maximum number of ports is used on every cycle. Ports are written and read in round robin order. Test is pipelined in such way that writing starts on the first cycle and reading starts when all the registers can be read without stall cycles.

Definition at line 339 of file RFTestbenchGenerator.cc.

                                     {
 
    RegisterFileState& simRF = msm_->registerFileState(RF_NAME_);
    assert(&simRF != &NullRegisterFileState::instance());
 
    PortDataArray inputData;
    PortDataArray inputOpcode;
    PortDataArray inputLoad;
 
    PortDataArray outputData;
    PortDataArray outputOpcode;
    PortDataArray outputLoad;
 
    // initialize a random number generator for the stimuli
    boost::uniform_int<> distribution(INT_MIN, INT_MAX);
    boost::mt19937 rng;
    rng.seed(time(NULL));
    boost::variate_generator<boost::mt19937&, boost::uniform_int<> >
        randomNumber(rng, distribution);
   
    // Number of cycles needed to write to all registers
    int fillCycles = 0;
    if (rfArch_->size() >= rfArch_->writePortCount()) {
        double size = rfArch_->size();
        double ports = rfArch_->writePortCount();
        fillCycles = static_cast<int>(ceil(size/ports));
    } else {
        // RF has more write ports than registers
        fillCycles = rfArch_->size();
    }
    // Number of cycles needed to read all registers (this includes flush 
    // cycles)
    int readCycles =
        static_cast<int>(ceil(rfArch_->size() / rfArch_->readPortCount()));
    
    // Number of cycles needed to wait before we can start reading from RF
    int outputWaitCycles = 0;
    // Number of cycles needed to read rest of the register after fill cycles
    int pipelineFlushCycles = 0;
    if (fillCycles > readCycles) {
        pipelineFlushCycles = rfArch_->latency();
        // total cycles - read cycles
        outputWaitCycles = fillCycles + pipelineFlushCycles - readCycles;
    } else {
        pipelineFlushCycles = rfArch_->latency() + (readCycles - fillCycles);
        outputWaitCycles = rfArch_->latency();
    }
 
    // port index and register where next input should be written to
    int wrPortIndex = 0;
    int wrRegIndex = 0;
    // port index and register where next output should be read from
    int rdPortIndex = 0;
    int rdRegIndex = 0;
    // port index and register where next output load is written to
    int rdLoadPortIndex = 0;
    int rdLoadRegIndex = 0;
 
    // Write data to registers and also start reading them when possible
    for (int i = 0; i < fillCycles; i++) {
        // Handle output first because register state is updated immediately
        if (i < outputWaitCycles) {
            for (int j = 0; j < rfArch_->readPortCount(); j++) {
                string portName = outputPorts_.at(j);
                outputData[portName].push_back(0);
            }
        } else {
            for (int j = 0; j < rfArch_->readPortCount(); j++) {
                string portName = outputPorts_.at(rdPortIndex);
                outputData[portName].push_back(
                    simRF.registerState(rdRegIndex).value().unsignedValue());
                // round robin regs and ports
                rdRegIndex++;
                rdRegIndex = rdRegIndex % rfArch_->size();
                rdPortIndex++;
                rdPortIndex = rdPortIndex % rfArch_->readPortCount();
            }
        }
 
        // write output load and opcode signals
        if ( i < (outputWaitCycles - rfArch_->latency())) {
            for (int j = 0; j < rfArch_->readPortCount(); j++) {
                string opcodePort = outputOpcodePorts_.at(j);
                string loadPort =  outputLoadPorts_.at(j);
                outputOpcode[opcodePort].push_back(0);
                outputLoad[loadPort].push_back(0);
            }
        } else {
           for (int j = 0; j < rfArch_->readPortCount(); j++) {
                string opcodePort = outputOpcodePorts_.at(rdLoadPortIndex);
                string loadPort =  outputLoadPorts_.at(rdLoadPortIndex);
                outputOpcode[opcodePort].push_back(rdLoadRegIndex);
                outputLoad[loadPort].push_back(1);
                // round robin regs and ports
                rdLoadRegIndex++;
                rdLoadRegIndex = rdLoadRegIndex % rfArch_->size();
                rdLoadPortIndex++;
                rdLoadPortIndex = rdLoadPortIndex % rfArch_->readPortCount();
           } 
        }
            
        
        // write inputs
        for (int j = 0; j < rfArch_->writePortCount(); j++) {
            int nopPortIndex = wrPortIndex;
            // write only to as many ports per cycle as possible
            // and write only once to every register
            if (j < rfArch_->maxWrites() && wrRegIndex < rfArch_->size()) {
                uint32_t stimulus = (uint32_t)randomNumber();
                const int portWidth = rfArch_->width();
                SimValue simStim(portWidth);
                stimulus = (stimulus << (32 - portWidth) >> (32 - portWidth));
                simStim = stimulus;
                simRF.registerState(wrRegIndex).setValue(simStim);
 
                string portName = inputPorts_.at(wrPortIndex);
                inputData[portName].push_back(stimulus);
 
                string opcodePort = inputOpcodePorts_.at(wrPortIndex);
                uint32_t opcode = static_cast<uint32_t>(wrRegIndex);
                inputOpcode[opcodePort].push_back(opcode);
 
                string loadPort = inputLoadPorts_.at(wrPortIndex);
                uint32_t load = 1;
                inputLoad[loadPort].push_back(load);
 
                wrRegIndex++;
                // use round robin for write ports
                wrPortIndex++;
                wrPortIndex = wrPortIndex % rfArch_->writePortCount();
            } else {
                // write nop to other ports
                uint32_t stimulus = 0;
                uint32_t opcode = 0;
                uint32_t load = 0;
                
                string portName = inputPorts_.at(nopPortIndex);
                inputData[portName].push_back(stimulus);
                
                string opcodePort = inputOpcodePorts_.at(nopPortIndex);
                inputOpcode[opcodePort].push_back(opcode);
                string loadPort = inputLoadPorts_.at(nopPortIndex);
                inputLoad[loadPort].push_back(load);
 
                // round robin
                wrPortIndex++;
                wrPortIndex = wrPortIndex % rfArch_->writePortCount();
            }
        }
    }
 
    // No more data to be written, read rest of the registers
    for (int i = 0; i < pipelineFlushCycles; i++) {
        for (int j = 0; j < rfArch_->writePortCount(); j++) {
            // write nop to write ports
            uint32_t stimulus = 0;
            uint32_t opcode = 0;
            uint32_t load = 0;
                
            string portName = inputPorts_.at(j);
            inputData[portName].push_back(stimulus);
                
            string opcodePort = inputOpcodePorts_.at(j);
            inputOpcode[opcodePort].push_back(opcode);
            string loadPort = inputLoadPorts_.at(j);
            inputLoad[loadPort].push_back(load);
        }
        // write output load signals
        for (int j = 0; j < rfArch_->readPortCount(); j++) {
            string opcodePort = outputOpcodePorts_.at(rdLoadPortIndex);
            string loadPort =  outputLoadPorts_.at(rdLoadPortIndex);
            outputOpcode[opcodePort].push_back(rdLoadRegIndex);
            outputLoad[loadPort].push_back(1);
            // round robin regs and ports
            rdLoadRegIndex++;
            rdLoadRegIndex = rdLoadRegIndex % rfArch_->size();
            rdLoadPortIndex++;
            rdLoadPortIndex = rdLoadPortIndex % rfArch_->readPortCount();
        } 
        // write output data, opcodes and loads
        for (int j = 0; j < rfArch_->readPortCount(); j++) {
            string portName = outputPorts_.at(rdPortIndex);
            outputData[portName].push_back(
                simRF.registerState(rdRegIndex).value().unsignedValue());
            // round robin regs and ports
            rdRegIndex++;
            rdRegIndex = rdRegIndex % rfArch_->size();
            rdPortIndex++;
            rdPortIndex = rdPortIndex % rfArch_->readPortCount();
        }
    }
 
    createStimulusArrays(inputData, inputOpcode, inputLoad, outputData,
                         outputOpcode, outputLoad);
 
    int totalCycleCount = fillCycles + pipelineFlushCycles;
    writeTbConstants(totalCycleCount, outputWaitCycles);
}

References assert, createStimulusArrays(), inputLoadPorts_, inputOpcodePorts_, inputPorts_, NullRegisterFileState::instance(), HDB::RFArchitecture::latency(), msm_, outputLoadPorts_, outputOpcodePorts_, outputPorts_, HDB::RFArchitecture::readPortCount(), MachineState::registerFileState(), RegisterFileState::registerState(), RF_NAME_, rfArch_, RegisterState::setValue(), HDB::RFArchitecture::size(), SimValue::unsignedValue(), RegisterState::value(), HDB::RFArchitecture::width(), HDB::RFArchitecture::writePortCount(), and TestbenchGenerator::writeTbConstants().

Referenced by generateTestbench().

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createStimulusArrays()

void RFTestbenchGenerator::createStimulusArrays ( PortDataArray &  inputData, PortDataArray &  inputOpcode, PortDataArray &  inputLoad, PortDataArray &  outputData, PortDataArray &  outputOpcode, PortDataArray &  outputLoad  )

private

Writes input, output and control signal data to output streams

Parameters

inputData	Array containing input ports and their values
inputOpcode	Array containing input port opcode ports and their values
inputLoad	Array containing input port load ports and their values
outputData	Array containing output ports and their values
outputOpcode	Array containing output port opcode ports and their values
outputLoad	Array containing output port load ports and their values

Definition at line 606 of file RFTestbenchGenerator.cc.

                               {
 
    int portWidth = rfArch_->width();
    writeDataArrays(inputArrayStream(), inputData, portWidth);
    writeDataArrays(outputArrayStream(), outputData, portWidth);
 
    int loadWidth = 1;
    writeDataArrays(loadArrayStream(), inputLoad, loadWidth);
    writeDataArrays(loadArrayStream(), outputLoad, loadWidth);
 
    int opcodeWidth = opcodePortWidth();
    writeDataArrays(opcodeArrayStream(), inputOpcode, opcodeWidth);
    writeDataArrays(opcodeArrayStream(), outputOpcode, opcodeWidth);
}

References TestbenchGenerator::inputArrayStream(), TestbenchGenerator::loadArrayStream(), TestbenchGenerator::opcodeArrayStream(), opcodePortWidth(), TestbenchGenerator::outputArrayStream(), rfArch_, HDB::RFArchitecture::width(), and writeDataArrays().

Referenced by createStimulus().

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createTbCode()

void RFTestbenchGenerator::createTbCode ( )

private

Writes the testbench main process code

Definition at line 542 of file RFTestbenchGenerator.cc.

                                   {
    
    // input ports
    for (int i = 0; i < rfArch_->writePortCount(); i++) {
        string portName = inputPorts_.at(i);
        string loadPort = inputLoadPorts_.at(i);
        string opcodePort = inputOpcodePorts_.at(i);
        
        tbCodeStream()
            << INDENT INDENT << portName << " <= " << portName << "_data("
            << "current_cycle);" << std::endl
            << INDENT INDENT << loadPort << " <= " << loadPort 
            <<"_data(current_cycle);" << std::endl
            << INDENT INDENT << opcodePort << " <= " << opcodePort 
            << "_data(current_cycle);" << std::endl;
    }
    // output port load and opcode signals
    for (int i = 0; i < rfArch_->readPortCount(); i++) {       
        string loadPort = outputLoadPorts_.at(i);
        string opcodePort = outputOpcodePorts_.at(i);
 
        tbCodeStream() 
            << INDENT INDENT << loadPort << " <= " << loadPort 
            <<"_data(current_cycle);" << std::endl
            << INDENT INDENT << opcodePort << " <= " << opcodePort 
            << "_data(current_cycle);" << std::endl;
    }
    // output ports
    tbCodeStream()
        << std::endl << std::endl << INDENT INDENT 
        << "if current_cycle >= IGNORE_OUTPUT_COUNT then" << std::endl;
    for (int i = 0; i < rfArch_->readPortCount(); i++) {
        string portName = outputPorts_.at(i);
        tbCodeStream() 
            << INDENT INDENT INDENT 
            << "assert " << portName << " = " << portName << "_data"
            << "(current_cycle)" << std::endl
            << INDENT INDENT INDENT INDENT 
            << "report lf & \"TCE Assert: Verification failed at cycle \" "
            << "& str(current_cycle, 10)" << std::endl
            << INDENT INDENT INDENT INDENT <<"& \" output: \" "
            << "& str(conv_integer(signed(" << portName << ")), 10)" 
            << std::endl
            << INDENT INDENT INDENT INDENT << "& " 
            << "\" expected: \" & str(conv_integer(signed(" << portName
            << "_data(current_cycle))), 10)  severity error;" 
            << std::endl << std::endl;
    }
    tbCodeStream() << INDENT INDENT << "end if;" << std::endl;
}

References INDENT, inputLoadPorts_, inputOpcodePorts_, inputPorts_, outputLoadPorts_, outputOpcodePorts_, outputPorts_, HDB::RFArchitecture::readPortCount(), rfArch_, TestbenchGenerator::tbCodeStream(), and HDB::RFArchitecture::writePortCount().

Referenced by generateTestbench().

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createTbInstantiation()

void RFTestbenchGenerator::createTbInstantiation ( )

private

Creates component declaration, connection signals and connects RF component to testbench

Definition at line 168 of file RFTestbenchGenerator.cc.

                                            {
 
    bindingStream() 
        << INDENT << "for tested_rf_0 : rf_under_test use entity work.";
    bindingStream() << rfImpl_->moduleName() << ";" << std::endl;
    
    declarationStream()
        << INDENT << "component rf_under_test" << std::endl;
    instantiationStream()
        << INDENT << "tested_rf_0\t:\trf_under_test " << std::endl;
 
    string sizeGeneric = rfImpl_->sizeParameter();
    string widthGeneric = rfImpl_->widthParameter();
    if (!sizeGeneric.empty() || !widthGeneric.empty()) {
        declarationStream()
            << INDENT INDENT << "generic(" << std::endl;
        instantiationStream()
            << INDENT INDENT << "generic map (" << std::endl;
        if (!sizeGeneric.empty()) {
            declarationStream()
                << INDENT INDENT INDENT << sizeGeneric
                << "\t: integer := " << rfArch_->size();
            instantiationStream()
                << INDENT INDENT INDENT  << sizeGeneric << " => " 
                << rfArch_->size();
            if (!widthGeneric.empty()) {
                declarationStream() << ";" << std::endl;
                instantiationStream() << "," << std::endl;
            }
        }
 
        if (!widthGeneric.empty()) {
            declarationStream()
                << INDENT INDENT INDENT << widthGeneric
                << "\t: integer := " << rfArch_->width();
            instantiationStream()
                << INDENT INDENT INDENT << widthGeneric << " => " 
                << rfArch_->width();
        }
        declarationStream()
            << ");" << std::endl;
        instantiationStream()
            << ")" << std::endl;
    }
 
    declarationStream()
        << INDENT INDENT << "port(" << std::endl;
    instantiationStream()
        << INDENT INDENT << "port map (" << std::endl;
    
    const int portWidth = rfArch_->width();
    int opcodeWidth = opcodePortWidth();
    for (int i = 0; i < rfArch_->writePortCount(); i++) {
        // data port
         declarationStream() 
             << INDENT INDENT << inputPorts_.at(i) << "\t: "
             << "in std_logic_vector(" << portWidth
             << "-1 downto 0);" << std::endl;    
         // load port
         declarationStream() 
             << INDENT INDENT << inputLoadPorts_.at(i) << "\t: "
             << "in std_logic;" << std::endl;
         // opcode port
         declarationStream()
             << INDENT INDENT << inputOpcodePorts_.at(i) << "\t: "
             << "in std_logic_vector(" << opcodeWidth
             << "-1 downto 0);" << std::endl;
 
         signalStream()
            << INDENT << "signal " << inputPorts_.at(i) << "\t: "
            << "std_logic_vector(" << portWidth << "-1 downto 0);" 
            << std::endl;
         signalStream()
             << INDENT << "signal " << inputLoadPorts_.at(i)
             << "\t: std_logic_vector(1-1 downto 0);" << std::endl;
         signalStream()
             << INDENT << "signal " << inputOpcodePorts_.at(i) << "\t: "
             << "std_logic_vector(" << opcodeWidth << "-1 downto 0);"
             << std::endl;
 
         instantiationStream()
            << INDENT INDENT INDENT << inputPorts_.at(i) << " => " 
            << inputPorts_.at(i) << "," << std::endl;
         instantiationStream()
             << INDENT INDENT INDENT << inputLoadPorts_.at(i) << " => " 
             << inputLoadPorts_.at(i) << "(0)," << std::endl;
         instantiationStream()
             << INDENT INDENT INDENT << inputOpcodePorts_.at(i) << " => " 
             << inputOpcodePorts_.at(i) << "," << std::endl;
    }
 
    for (int i = 0; i < rfArch_->readPortCount(); i++) {
        declarationStream() 
             << INDENT INDENT << outputPorts_.at(i) << "\t: "
             << "out std_logic_vector(" << portWidth
             << "-1 downto 0);" << std::endl;    
         // load port
         declarationStream() 
             << INDENT INDENT << outputLoadPorts_.at(i) << "\t: "
             << "in std_logic;" << std::endl;
         // opcode port
         declarationStream()
             << INDENT INDENT << outputOpcodePorts_.at(i) << "\t: "
             << "in std_logic_vector(" << opcodeWidth
             << "-1 downto 0);" << std::endl;
         
         signalStream()
            << INDENT << "signal " << outputPorts_.at(i) << "\t: "
            << "std_logic_vector(" << portWidth << "-1 downto 0);" 
            << std::endl;
         signalStream()
             << INDENT << "signal " << outputLoadPorts_.at(i)
             << "\t: std_logic_vector(1-1 downto 0);" << std::endl;
         signalStream()
             << INDENT << "signal " << outputOpcodePorts_.at(i) << "\t: "
             << "std_logic_vector(" << opcodeWidth << "-1 downto 0);"
             << std::endl;
 
         instantiationStream()
            << INDENT INDENT INDENT << outputPorts_.at(i) << " => " 
            << outputPorts_.at(i) << "," << std::endl;
         instantiationStream()
             << INDENT INDENT INDENT << outputLoadPorts_.at(i) << " => "
             << outputLoadPorts_.at(i) << "(0)," << std::endl;
         instantiationStream()
             << INDENT INDENT INDENT << outputOpcodePorts_.at(i) << " => " 
             << outputOpcodePorts_.at(i) << "," << std::endl;  
    }
    instantiationStream() 
        << INDENT INDENT INDENT
        << rfImpl_->clkPort() << " => " << rfImpl_->clkPort() 
        << "," << std::endl
        << INDENT INDENT INDENT
        << rfImpl_->rstPort() << " => " << rfImpl_->rstPort() 
        << "," << std::endl
        << INDENT INDENT INDENT
        << rfImpl_->glockPort() << " => " << rfImpl_->glockPort() 
        << ");";
 
    declarationStream()
        << INDENT INDENT << rfImpl_->glockPort() << "\t: in  std_logic;" 
        << std::endl
        << INDENT INDENT << rfImpl_->rstPort() << "\t: in  std_logic;" 
        << std::endl
        << INDENT INDENT << rfImpl_->clkPort() << "\t: in  std_logic);" 
        << std::endl
        << INDENT << "end component;" 
        << std::endl;
    
    signalStream()
        << INDENT << "signal " << rfImpl_->glockPort() << "\t: std_logic;" 
        << std::endl
        << INDENT << "signal " << rfImpl_->rstPort() << "\t: std_logic;" 
        << std::endl
        << INDENT << "signal " << rfImpl_->clkPort() << "\t: std_logic;" 
        << std::endl;
    
}

References TestbenchGenerator::bindingStream(), HDB::HWBlockImplementation::clkPort(), TestbenchGenerator::declarationStream(), HDB::HWBlockImplementation::glockPort(), INDENT, inputLoadPorts_, inputOpcodePorts_, inputPorts_, TestbenchGenerator::instantiationStream(), HDB::HWBlockImplementation::moduleName(), opcodePortWidth(), outputLoadPorts_, outputOpcodePorts_, outputPorts_, HDB::RFArchitecture::readPortCount(), rfArch_, rfImpl_, HDB::HWBlockImplementation::rstPort(), TestbenchGenerator::signalStream(), HDB::RFArchitecture::size(), HDB::RFImplementation::sizeParameter(), HDB::RFArchitecture::width(), HDB::RFImplementation::widthParameter(), and HDB::RFArchitecture::writePortCount().

Referenced by generateTestbench().

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generateTestbench()

void RFTestbenchGenerator::generateTestbench ( std::ofstream &  file )

virtual

Creates the testbench and writes it to the given filestream

Parameters

file	Filestream where the testbench is written

Implements TestbenchGenerator.

Definition at line 89 of file RFTestbenchGenerator.cc.

                                                         {
 
    rfImpl_ = &rfEntry_->implementation();
    rfArch_ = &rfEntry_->architecture();
 
    createMachineState();
    parseRfPorts();
    createStimulus();
    createTbInstantiation();
    createTbCode();
    writeTestbench(file, rfImpl_);
}

References HDB::RFEntry::architecture(), createMachineState(), createStimulus(), createTbCode(), createTbInstantiation(), HDB::RFEntry::implementation(), parseRfPorts(), rfArch_, rfEntry_, rfImpl_, and TestbenchGenerator::writeTestbench().

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opcodePortWidth()

int RFTestbenchGenerator::opcodePortWidth ( ) const

private

Definition at line 628 of file RFTestbenchGenerator.cc.

                                            {
 
    int width = 0;
    if (rfArch_->size() > 1) {
        unsigned int biggestIndex = rfArch_->size()-1;
        width = MathTools::requiredBits(biggestIndex);
    } else {
        width = 1;
    }
    return width;
}

References MathTools::requiredBits(), rfArch_, and HDB::RFArchitecture::size().

Referenced by createStimulusArrays(), and createTbInstantiation().

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parseRfPorts()

void RFTestbenchGenerator::parseRfPorts ( )

private

Definition at line 142 of file RFTestbenchGenerator.cc.

                                   {
 
     for (int i = 0; i < rfImpl_->portCount(); i++) {
         string portName = rfImpl_->port(i).name();
         string opcodePort = rfImpl_->port(i).opcodePort();
         string loadPort =  rfImpl_->port(i).loadPort();
         if (rfImpl_->port(i).direction() == HDB::IN) {
             inputPorts_.push_back(portName);
             inputOpcodePorts_.push_back(opcodePort);
             inputLoadPorts_.push_back(loadPort);
         } else if (rfImpl_->port(i).direction() == HDB::OUT) {
             outputPorts_.push_back(portName);
             outputOpcodePorts_.push_back(opcodePort);
             outputLoadPorts_.push_back(loadPort);
         } else {
             assert(false && "RF port implementation does not have direction");
         }
     }
 }

References assert, HDB::RFPortImplementation::direction(), HDB::IN, inputLoadPorts_, inputOpcodePorts_, inputPorts_, HDB::PortImplementation::loadPort(), HDB::PortImplementation::name(), HDB::RFPortImplementation::opcodePort(), HDB::OUT, outputLoadPorts_, outputOpcodePorts_, outputPorts_, HDB::RFImplementation::port(), HDB::RFImplementation::portCount(), and rfImpl_.

Referenced by generateTestbench().

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writeDataArrays()

void RFTestbenchGenerator::writeDataArrays ( std::ostringstream &  stream, PortDataArray &  array, int  portWidth  )

private

Write one PortDataArray to output stream

Parameters

stream	Output stream
array	Array to be written
portWidth	Width of the output port

Definition at line 648 of file RFTestbenchGenerator.cc.

                    {
 
    for (PortDataArray::iterator i = array.begin(); i != array.end(); i++) {
        string portName = i->first;
        vector<uint32_t> data = i->second;
        writeStimulusArray(stream, data, portName, portWidth);
    }
}

References TestbenchGenerator::writeStimulusArray().

Referenced by createStimulusArrays().

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Member Data Documentation

inputLoadPorts_

std::vector<std::string> RFTestbenchGenerator::inputLoadPorts_

private

Definition at line 97 of file RFTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseRfPorts().

inputOpcodePorts_

std::vector<std::string> RFTestbenchGenerator::inputOpcodePorts_

private

Definition at line 98 of file RFTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseRfPorts().

inputPorts_

std::vector<std::string> RFTestbenchGenerator::inputPorts_

private

Definition at line 96 of file RFTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseRfPorts().

machine_

TTAMachine::Machine* RFTestbenchGenerator::machine_

private

Definition at line 93 of file RFTestbenchGenerator.hh.

Referenced by createMachineState(), and ~RFTestbenchGenerator().

machRf_

TTAMachine::RegisterFile* RFTestbenchGenerator::machRf_

private

Definition at line 90 of file RFTestbenchGenerator.hh.

Referenced by createMachineState().

memSystem_

MemorySystem* RFTestbenchGenerator::memSystem_

private

Definition at line 94 of file RFTestbenchGenerator.hh.

Referenced by createMachineState(), and ~RFTestbenchGenerator().

msm_

MachineState* RFTestbenchGenerator::msm_

private

Definition at line 92 of file RFTestbenchGenerator.hh.

Referenced by createMachineState(), createStimulus(), and ~RFTestbenchGenerator().

outputLoadPorts_

std::vector<std::string> RFTestbenchGenerator::outputLoadPorts_

private

Definition at line 100 of file RFTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseRfPorts().

outputOpcodePorts_

std::vector<std::string> RFTestbenchGenerator::outputOpcodePorts_

private

Definition at line 101 of file RFTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseRfPorts().

outputPorts_

std::vector<std::string> RFTestbenchGenerator::outputPorts_

private

Definition at line 99 of file RFTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseRfPorts().

RF_NAME_

const std::string RFTestbenchGenerator::RF_NAME_ = "testRF"

staticprivate

Definition at line 103 of file RFTestbenchGenerator.hh.

Referenced by createMachineState(), and createStimulus().

rfArch_

HDB::RFArchitecture* RFTestbenchGenerator::rfArch_

private

Definition at line 89 of file RFTestbenchGenerator.hh.

Referenced by createMachineState(), createStimulus(), createStimulusArrays(), createTbCode(), createTbInstantiation(), generateTestbench(), and opcodePortWidth().

rfEntry_

HDB::RFEntry* RFTestbenchGenerator::rfEntry_

private

Definition at line 87 of file RFTestbenchGenerator.hh.

Referenced by generateTestbench().

rfImpl_

HDB::RFImplementation* RFTestbenchGenerator::rfImpl_

private

Definition at line 88 of file RFTestbenchGenerator.hh.

Referenced by createTbInstantiation(), generateTestbench(), and parseRfPorts().

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The documentation for this class was generated from the following files:

• RFTestbenchGenerator.hh
• RFTestbenchGenerator.cc