#include <Stratix3DevKitIntegrator.hh>

Inheritance diagram for Stratix3DevKitIntegrator:

Collaboration diagram for Stratix3DevKitIntegrator:

Public Member Functions
	Stratix3DevKitIntegrator ()

	Stratix3DevKitIntegrator (const TTAMachine::Machine machine, const IDF::MachineImplementation idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)

virtual	~Stratix3DevKitIntegrator ()

virtual void	integrateProcessor (const ProGe::NetlistBlock *ttaCore)

virtual TCEString	deviceFamily () const

virtual void	setDeviceFamily (TCEString devFamily)

virtual TCEString	devicePackage () const

virtual TCEString	deviceSpeedClass () const

virtual int	targetClockFrequency () const

virtual void	printInfo (std::ostream &stream) const

Public Member Functions inherited from AlteraIntegrator
	AlteraIntegrator ()

	AlteraIntegrator (const TTAMachine::Machine machine, const IDF::MachineImplementation idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString entityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)

virtual	~AlteraIntegrator ()

Public Member Functions inherited from PlatformIntegrator
	PlatformIntegrator ()

	PlatformIntegrator (const TTAMachine::Machine machine, const IDF::MachineImplementation idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)

virtual	~PlatformIntegrator ()

void	setDeviceName (TCEString devName)

TCEString	deviceName () const

const ProGe::NetlistBlock &	progeBlock () const

const ProGe::NetlistBlock &	toplevelBlock () const

void	setSharedOutputDir (const TCEString &sharedDir)

TCEString	outputPath () const

TCEString	outputFilePath (TCEString fileName, bool absolute=false) const

TCEString	coreEntityName () const

const TTAMachine::Machine *	machine () const

const IDF::MachineImplementation *	idf () const

const MemInfo &	imemInfo () const

const MemInfo &	dmemInfo (TTAMachine::AddressSpace *as) const

const MemInfo &	dmemInfo (int index) const

int	dmemCount () const

ProGe::NetlistPort *	clockPort () const

ProGe::NetlistPort *	resetPort () const

Protected Member Functions
virtual TCEString	pinTag () const

virtual bool	chopTaggedSignals () const

virtual ProjectFileGenerator *	projectFileGenerator () const

Protected Member Functions inherited from AlteraIntegrator
virtual MemoryGenerator &	imemInstance (MemInfo imem, int coreId)

virtual MemoryGenerator &	dmemInstance (MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Member Functions inherited from PlatformIntegrator
ProGe::NetlistBlock *	integratorBlock ()

virtual void	initPlatformNetlist (const ProGe::NetlistBlock *progeBlock)

virtual bool	integrateCore (const ProGe::NetlistBlock &cores, int coreId)

virtual void	exportUnconnectedPorts (int coreId)

virtual void	connectToplevelPort (const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")

virtual bool	hasPinTag (const TCEString &signal) const

void	copyProgeBlockToNetlist (const ProGe::NetlistBlock *progeBlock)

virtual bool	createMemories (int coreId)

virtual bool	generateMemory (MemoryGenerator &memGen, std::vector< TCEString > &generatedFiles, int memIndex, int coreId)

virtual void	writeNewToplevel ()

void	addProGeFiles () const

TCEString	programName () const

TCEString	progeFilePath (TCEString fileName, bool absolute=false) const

TCEString	chopSignalToTag (const TCEString &original, const TCEString &tag) const

void	progeOutputHdlFiles (std::vector< TCEString > &files) const

std::ostream &	warningStream () const

std::ostream &	errorStream () const

TCEString	platformEntityName () const

void	parseDataMemories ()

void	clearDataMemories ()

MemInfo	readLsuParameters (const TTAMachine::FunctionUnit &lsu)

Private Member Functions
void	generatePinMap ()

void	mapToplevelPorts ()

void	addSignalMapping (const TCEString &signal)

Private Attributes
QuartusProjectGenerator *	quartusGen_

PlatInt::PinMap	stratix3Pins_

Static Private Attributes
static const TCEString	DEVICE_FAMILY_ = "Stratix III"

static const TCEString	DEVICE_NAME_ = "EP3SL150F1152C2"

static const TCEString	DEVICE_PACKAGE_ = "F1152"

static const TCEString	DEVICE_SPEED_CLASS_ = "2"

static const TCEString	PIN_TAG_ = "STRATIXIII"

static const int	DEFAULT_FREQ_ = 125

Additional Inherited Members
Static Protected Attributes inherited from PlatformIntegrator
static const TCEString	TTA_CORE_CLK = "clk"

static const TCEString	TTA_CORE_RSTX = "rstx"

Detailed Description

Definition at line 44 of file Stratix3DevKitIntegrator.hh.

Constructor & Destructor Documentation

◆ Stratix3DevKitIntegrator() [1/2]

Stratix3DevKitIntegrator::Stratix3DevKitIntegrator ( )

Definition at line 59 of file Stratix3DevKitIntegrator.cc.

                                                   :
     AlteraIntegrator(), quartusGen_(NULL) {
 }

◆ Stratix3DevKitIntegrator() [2/2]

Stratix3DevKitIntegrator::Stratix3DevKitIntegrator	(	const TTAMachine::Machine *	machine,
		const IDF::MachineImplementation *	idf,
		ProGe::HDL	hdl,
		TCEString	progeOutputDir,
		TCEString	coreEntityName,
		TCEString	outputDir,
		TCEString	programName,
		int	targetClockFreq,
		std::ostream &	warningStream,
		std::ostream &	errorStream,
		const MemInfo &	imem,
		MemType	dmemType
	)

Definition at line 64 of file Stratix3DevKitIntegrator.cc.

                      :
     AlteraIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
                      outputDir, programName, targetClockFreq, warningStream,
                      errorStream, imem, dmemType),
     quartusGen_(new QuartusProjectGenerator(coreEntityName, this)) {
     setDeviceName(DEVICE_NAME_);
 }

References DEVICE_NAME_, and PlatformIntegrator::setDeviceName().

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◆ ~Stratix3DevKitIntegrator()

Stratix3DevKitIntegrator::~Stratix3DevKitIntegrator ( )

virtual

Definition at line 85 of file Stratix3DevKitIntegrator.cc.

                                                     {
  
     for (PlatInt::PinMap::iterator iter = stratix3Pins_.begin();
          iter != stratix3Pins_.end(); iter++) {
         if (iter->second != NULL) {
             for (unsigned int i = 0; i < iter->second->size(); i++) {
                 delete iter->second->at(i);
             }
             delete iter->second;
         }
     }
     if (quartusGen_ != NULL) {
         delete quartusGen_;
     }
 }

References quartusGen_, and stratix3Pins_.

Member Function Documentation

◆ addSignalMapping()

void Stratix3DevKitIntegrator::addSignalMapping ( const TCEString & signal )

private

Definition at line 221 of file Stratix3DevKitIntegrator.cc.

                                                                   {
     
     if (stratix3Pins_.find(signal) == stratix3Pins_.end()) {
         warningStream() << "Warning: didn't find mapping for signal name "
                         << signal << endl;
         return;
     }
  
     SignalMappingList* mappings = stratix3Pins_.find(signal)->second;
     for (unsigned int i = 0; i < mappings->size(); i++) {
         quartusGen_->addSignalMapping(*mappings->at(i));
     }
 }

References ProjectFileGenerator::addSignalMapping(), quartusGen_, stratix3Pins_, and PlatformIntegrator::warningStream().

Referenced by mapToplevelPorts().

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◆ chopTaggedSignals()

bool Stratix3DevKitIntegrator::chopTaggedSignals ( ) const

protectedvirtual

Implements PlatformIntegrator.

Definition at line 198 of file Stratix3DevKitIntegrator.cc.

                                                   {
  
     return true;
 }

◆ deviceFamily()

TCEString Stratix3DevKitIntegrator::deviceFamily ( ) const

virtual

Returns the FPGA device family

Implements PlatformIntegrator.

Definition at line 127 of file Stratix3DevKitIntegrator.cc.

                                              {
     
     return DEVICE_FAMILY_;
 }

References DEVICE_FAMILY_.

◆ devicePackage()

TCEString Stratix3DevKitIntegrator::devicePackage ( ) const

virtual

Returns the device package name

Implements PlatformIntegrator.

Definition at line 146 of file Stratix3DevKitIntegrator.cc.

                                               {
  
     return DEVICE_PACKAGE_;
 }

References DEVICE_PACKAGE_.

◆ deviceSpeedClass()

TCEString Stratix3DevKitIntegrator::deviceSpeedClass ( ) const

virtual

Returns the device speed class

Implements PlatformIntegrator.

Definition at line 153 of file Stratix3DevKitIntegrator.cc.

                                                  {
  
     return DEVICE_SPEED_CLASS_;
 }

References DEVICE_SPEED_CLASS_.

◆ generatePinMap()

void Stratix3DevKitIntegrator::generatePinMap ( )

private

Definition at line 237 of file Stratix3DevKitIntegrator.cc.

                                          {
  
     // clk
     SignalMappingList* clk = new SignalMappingList;
     clk->push_back(new SignalMapping("PIN_B16","clk"));
     stratix3Pins_["clk"] = clk;
  
     // reset to push button CPU_RESET
     SignalMappingList* rstx = new SignalMappingList;
     rstx->push_back(new SignalMapping("PIN_AP5","rstx"));
     stratix3Pins_["rstx"] = rstx;
  
     // leds
     const TCEString led = PIN_TAG_+"_LED";
     SignalMappingList* ledMapping = new SignalMappingList;
     ledMapping->push_back(new SignalMapping("PIN_F21", led+"[0]"));
     ledMapping->push_back(new SignalMapping("PIN_C23", led+"[1]"));
     ledMapping->push_back(new SignalMapping("PIN_B23", led+"[2]"));
     ledMapping->push_back(new SignalMapping("PIN_A23", led+"[3]"));
     ledMapping->push_back(new SignalMapping("PIN_D19", led+"[4]"));
     ledMapping->push_back(new SignalMapping("PIN_C19", led+"[5]"));
     ledMapping->push_back(new SignalMapping("PIN_F19", led+"[6]"));
     ledMapping->push_back(new SignalMapping("PIN_E19", led+"[7]"));
     stratix3Pins_[led] = ledMapping;
  
     // dip switches
     const TCEString sw = PIN_TAG_+"_USER_DIPSW";
     SignalMappingList* switchMapping = new SignalMappingList;
     switchMapping->push_back(new SignalMapping("PIN_B19", sw+"[0]"));
     switchMapping->push_back(new SignalMapping("PIN_A19", sw+"[1]"));
     switchMapping->push_back(new SignalMapping("PIN_C18", sw+"[2]"));
     switchMapping->push_back(new SignalMapping("PIN_A20", sw+"[3]"));
     switchMapping->push_back(new SignalMapping("PIN_K19", sw+"[4]"));
     switchMapping->push_back(new SignalMapping("PIN_J19", sw+"[5]"));
     switchMapping->push_back(new SignalMapping("PIN_L19", sw+"[6]"));
     switchMapping->push_back(new SignalMapping("PIN_L20", sw+"[7]"));
     stratix3Pins_[sw] = switchMapping;
  
     // push buttons
     const TCEString pb = PIN_TAG_+"_USER_PB";
     SignalMappingList* pbMapping = new SignalMappingList;
     pbMapping->push_back(new SignalMapping("PIN_B17", pb+"[0]"));
     pbMapping->push_back(new SignalMapping("PIN_A17", pb+"[1]"));
     pbMapping->push_back(new SignalMapping("PIN_A16", pb+"[2]"));
     pbMapping->push_back(new SignalMapping("PIN_K17", pb+"[3]"));
     stratix3Pins_[pb] = pbMapping;
     
 }

References PIN_TAG_, and stratix3Pins_.

Referenced by integrateProcessor().

◆ integrateProcessor()

void Stratix3DevKitIntegrator::integrateProcessor ( const ProGe::NetlistBlock * progeBlock )

virtual

Integrates the TTA core(s) generated by ProGe

Parameters

progeBlock The toplevel netlist block created by ProGe

Reimplemented from AlteraIntegrator.

Definition at line 103 of file Stratix3DevKitIntegrator.cc.

                                       {
  
     generatePinMap();
  
     initPlatformNetlist(ttaCore);
  
     const NetlistBlock& core = progeBlock();
     int coreId = -1;
     if (!integrateCore(core, coreId)) {
         return;
     }
  
     mapToplevelPorts();
  
     writeNewToplevel();
  
     addProGeFiles();
  
     projectFileGenerator()->writeProjectFiles();
 }

References PlatformIntegrator::addProGeFiles(), generatePinMap(), PlatformIntegrator::initPlatformNetlist(), PlatformIntegrator::integrateCore(), mapToplevelPorts(), PlatformIntegrator::progeBlock(), projectFileGenerator(), PlatformIntegrator::writeNewToplevel(), and ProjectFileGenerator::writeProjectFiles().

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◆ mapToplevelPorts()

void Stratix3DevKitIntegrator::mapToplevelPorts ( )

private

Definition at line 212 of file Stratix3DevKitIntegrator.cc.

                                            {
     NetlistBlock& tl = *integratorBlock();
     for (size_t i = 0; i < tl.portCount(); i++) {
         addSignalMapping(tl.port(i).name());
     }
 }

References addSignalMapping(), PlatformIntegrator::integratorBlock(), ProGe::NetlistPort::name(), ProGe::NetlistBlock::port(), and ProGe::NetlistBlock::portCount().

Referenced by integrateProcessor().

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◆ pinTag()

TCEString Stratix3DevKitIntegrator::pinTag ( ) const

protectedvirtual

Implements PlatformIntegrator.

Definition at line 191 of file Stratix3DevKitIntegrator.cc.

                                        {
  
     return PIN_TAG_;
 }

References PIN_TAG_.

◆ printInfo()

void Stratix3DevKitIntegrator::printInfo ( std::ostream & stream ) const

virtual

Prints information about the platform

Implements PlatformIntegrator.

Definition at line 172 of file Stratix3DevKitIntegrator.cc.

                                                             {
  
     stream
          << "Integrator name: Stratix3DevKit" << std::endl
          << "---------------------------------" << std::endl
          << "Integrates TTA core to Altera Stratix III Development Kit"
          << std::endl << "with" << DEVICE_NAME_ << " device." << std::endl
          << "Creates project files for QuartusII v8.0 program." << std::endl
          << "Supported instruction memory types are 'onchip' and 'vhdl_array."
          << std::endl
          << "Supported data memory type is 'onchip'."
          << std::endl
          << "Default clock frequency is 125 MHz." << std::endl
          << "Active low reset is connected to CPU RESET button."
          << std::endl << std::endl;
 }

References DEVICE_NAME_.

◆ projectFileGenerator()

ProjectFileGenerator * Stratix3DevKitIntegrator::projectFileGenerator ( ) const

protectedvirtual

Implements PlatformIntegrator.

Definition at line 205 of file Stratix3DevKitIntegrator.cc.

                                                      {
  
     return quartusGen_;
 }

References quartusGen_.

Referenced by integrateProcessor().

◆ setDeviceFamily()

void Stratix3DevKitIntegrator::setDeviceFamily ( TCEString devFamily )

virtual

Set the FPGA device family.

Intended for TTA IP integration. Integrator can device whether this overrides the default device family.

Implements PlatformIntegrator.

Definition at line 134 of file Stratix3DevKitIntegrator.cc.

                                                              {
     
     if (devFamily != DEVICE_FAMILY_) {
         warningStream() 
             << "Warning: Refusing to change device family!" << endl
             << "- Original device family: " << DEVICE_FAMILY_ << endl
             << "- New device family: " << devFamily << endl;
     }
 }

References DEVICE_FAMILY_, and PlatformIntegrator::warningStream().

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◆ targetClockFrequency()

int Stratix3DevKitIntegrator::targetClockFrequency ( ) const

virtual

Returns the target clock frequency in MHz

Reimplemented from PlatformIntegrator.

Definition at line 160 of file Stratix3DevKitIntegrator.cc.

                                                      {
  
     int freq = DEFAULT_FREQ_;
  
     if (PlatformIntegrator::targetClockFrequency() > 0) {
         freq = PlatformIntegrator::targetClockFrequency();
     }
     return freq;
 }