OpenASIP  2.0
Public Member Functions | Private Member Functions | Private Attributes | List of all members
llvm::TCEInstrInfo Class Reference

#include <TCEInstrInfo.hh>

Inheritance diagram for llvm::TCEInstrInfo:
Inheritance graph
Collaboration diagram for llvm::TCEInstrInfo:
Collaboration graph

Public Member Functions

 TCEInstrInfo (const TCETargetMachinePlugin *plugin)
 
virtual ~TCEInstrInfo ()
 
const InstrItineraryData * getInstrItineraryData () const
 
virtual const TargetRegisterInfo & getRegisterInfo () const
 
virtual unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
unsigned removeBranch (MachineBasicBlock &mbb, int *BytesRemoved=nullptr) const override
 
virtual bool BlockHasNoFallThrough (const MachineBasicBlock &MBB) const
 
virtual void storeRegToStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, unsigned srcReg, bool isKill, int frameIndex, const TargetRegisterClass *rc) const
 
virtual void storeRegToStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, Register srcReg, bool isKill, int frameIndex, const TargetRegisterClass *rc, const TargetRegisterInfo *) const override
 
virtual void loadRegFromStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, unsigned destReg, int frameIndex, const TargetRegisterClass *rc) const
 
virtual void loadRegFromStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, Register destReg, int frameIndex, const TargetRegisterClass *rc, const TargetRegisterInfo *) const override
 
virtual void copyPhysReg (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, const DebugLoc &DL, MCRegister destReg, MCRegister srcReg, bool KillSrc) const override
 
virtual bool reverseBranchCondition (llvm::SmallVectorImpl< llvm::MachineOperand > &cond) const override
 
virtual bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, llvm::SmallVectorImpl< llvm::MachineOperand > &cond, bool allowModify=false) const override
 
std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
 Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More...
 
virtual bool isPredicated (const MachineInstr &MI) const override
 
virtual bool isPredicable (const MachineInstr &MI) const override
 
virtual bool PredicateInstruction (MachineInstr &mi, ArrayRef< MachineOperand > cond) const override
 
virtual bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
 
virtual bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
virtual void insertCCBranch (MachineBasicBlock &mbb, MachineBasicBlock &tbb, ArrayRef< MachineOperand > cond, const DebugLoc &dl) const
 
virtual bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
virtual bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override
 
std::tuple< int, int > getPointerAdjustment (int offset) const
 
virtual DFAPacketizer * CreateTargetScheduleState (const TargetSubtargetInfo &) const override
 

Private Member Functions

int getMatchingCondBranchOpcode (int Opc, bool inverted) const
 
bool copyPhysVectorReg (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, const DebugLoc &DL, MCRegister destReg, MCRegister srcReg, bool killSrc) const
 

Private Attributes

InstrItineraryData InstrItins
 
const TCERegisterInfo ri_
 
const TCETargetMachinePlugin * plugin_
 

Detailed Description

!! Important !! ************* ON EVERY LLVM UPDATE CHECK THESE INTERFACES VERY CAREFULLY FROM include/llvm/Target/TargetInstrInfo.h

Compiler doesn warn or give error if parameter lists are changed. Many times also base class implementation works, but does not do very good job.

Definition at line 57 of file TCEInstrInfo.hh.

Constructor & Destructor Documentation

◆ TCEInstrInfo()

TCEInstrInfo::TCEInstrInfo ( const TCETargetMachinePlugin *  plugin)

Constructor.

Definition at line 73 of file TCEInstrInfo.cc.

74  :
75  TCEGenInstrInfo(TCE::ADJCALLSTACKDOWN, TCE::ADJCALLSTACKUP),
76  ri_(*this), plugin_(plugin) {
77 }

◆ ~TCEInstrInfo()

TCEInstrInfo::~TCEInstrInfo ( )
virtual

Destructor.

Definition at line 82 of file TCEInstrInfo.cc.

82  {
83 }

Member Function Documentation

◆ analyzeBranch()

bool TCEInstrInfo::analyzeBranch ( MachineBasicBlock &  mbb,
MachineBasicBlock *&  tbb,
MachineBasicBlock *&  fbb,
llvm::SmallVectorImpl< llvm::MachineOperand > &  cond,
bool  allowModify = false 
) const
overridevirtual

Analyzes branches of MBB.

Parameters
mbbMBB to analyze
tbbPuts the jump target or condition true target MBB here
fbbPuts the condition false target here, if not fall-thru
condputs the condition data (predcate reg and T/F) here
Returns
false if could analyze, true if could not analyze

Definition at line 449 of file TCEInstrInfo.cc.

453  {
454  if (mbb.empty()) {
455  return false;
456  }
457 
458  MachineBasicBlock::iterator i = mbb.end(); i--;
459 
460  MachineInstr& lastIns = *i;
461  switch (lastIns.getOpcode()) {
462  case TCE::TCEBRCOND:
463  tbb = lastIns.getOperand(1).getMBB();
464  cond.push_back(i->getOperand(0));
465  cond.push_back(MachineOperand::CreateImm(true));
466  return false;
467  case TCE::TCEBRICOND:
468  tbb = lastIns.getOperand(1).getMBB();
469  cond.push_back(i->getOperand(0));
470  cond.push_back(MachineOperand::CreateImm(false));
471  return false;
472  case TCE::TCEBRIND:
473  case TCE::TCEBR: {
474  // indirect jump cannot be analyzed
475  if (!lastIns.getOperand(0).isMBB()) {
476  return true;
477  }
478 
479  if (i == mbb.begin()) {
480  tbb = lastIns.getOperand(0).getMBB();
481  return false; // uncond jump only ins in mbb.
482  }
483  i--;
484  if (i->getOpcode() == TCE::TCEBRCOND) {
485  tbb = i->getOperand(1).getMBB();
486  fbb = lastIns.getOperand(0).getMBB();
487  cond.push_back(i->getOperand(0));
488  cond.push_back(MachineOperand::CreateImm(true));
489  return false;
490  }
491  if (i->getOpcode() == TCE::TCEBRICOND) {
492  tbb = i->getOperand(1).getMBB();
493  fbb = lastIns.getOperand(0).getMBB();
494  cond.push_back(i->getOperand(0));
495  cond.push_back(MachineOperand::CreateImm(false));
496  return false;
497  }
498  // two uncond branches not allowed
499  assert(i->getOpcode() != TCE::TCEBR);
500 
501  if (i->getDesc().isBranch()) {
502  tbb = i->getOperand(2).getMBB();
503  fbb = lastIns.getOperand(0).getMBB();
504  return plugin_->analyzeCCBranch(*i, cond);
505  } else { // only conditional branch.
506  tbb = lastIns.getOperand(0).getMBB();
507  return false;
508  }
509  }
510  default:
511  // if some another branch, it's unknown brach
512  // if not brannch, it's fallthourgh
513  if (lastIns.getDesc().isBranch()) {
514  tbb = lastIns.getOperand(2).getMBB();
515  return plugin_->analyzeCCBranch(lastIns, cond);
516  } else {
517  return false;
518  }
519  }
520  // should never be here
521  return true;
522 }

References llvm::TCETargetMachinePlugin::analyzeCCBranch(), assert, and plugin_.

Here is the call graph for this function:

◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > TCEInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock *  LoopBB) const
override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 554 of file TCEInstrInfo.cc.

554  {
555  return std::make_unique<TCEPipelinerLoopInfo>();
556 }

◆ BlockHasNoFallThrough()

bool TCEInstrInfo::BlockHasNoFallThrough ( const MachineBasicBlock &  MBB) const
virtual

Returns true if program control can't fall through the last instruction in the basic block, false otherwise.

Definition at line 196 of file TCEInstrInfo.cc.

196  {
197  /* Mips inspired */
198  if (MBB.empty()) return false;
199  switch (MBB.back().getOpcode()) {
200  case TCE::RETL: // Return.
201  case TCE::TCEBR: // Uncond branch.
202  case TCE::TCEBRIND: // Uncond indirect branch.
203  return true;
204  default: return false;
205  }
206 }

◆ ClobbersPredicate()

bool TCEInstrInfo::ClobbersPredicate ( MachineInstr &  MI,
std::vector< MachineOperand > &  Pred,
bool  SkipDead 
) const
overridevirtual

Definition at line 680 of file TCEInstrInfo.cc.

682  {
683  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
684  MachineOperand MO = MI.getOperand(oper);
685  if (MO.isReg() && MO.isDef()) {
686  const TargetRegisterClass* RC =
687  ri_.getMinimalPhysRegClass(MO.getReg());
688  if (RC == &TCE::GuardRegsRegClass || RC == &TCE::R1RegsRegClass) {
689  Pred.push_back(MO);
690  return true;
691  }
692  }
693  }
694  return false;
695 }

References ri_.

◆ copyPhysReg()

void TCEInstrInfo::copyPhysReg ( MachineBasicBlock &  mbb,
MachineBasicBlock::iterator  mbbi,
const DebugLoc &  DL,
MCRegister  destReg,
MCRegister  srcReg,
bool  killSrc 
) const
overridevirtual

Creates instruction for copying value from a register to another.

Parameters
mbbBasic block where the copy is done.
mbbiIterator to the place where the copy instruction is added.
srcRegRegister where the value is copied from.
destRegRegister where the value is copied to.
rcClass of the register to copy.

Definition at line 256 of file TCEInstrInfo.cc.

262 {
263  DebugLoc dl;
264  if (mbbi != mbb.end()) dl = mbbi->getDebugLoc();
265 /*
266  BuildMI(mbb, mbbi, dl,
267  get(plugin_->getRegCopy(destReg, srcReg)), destReg).
268  .addReg(SrcReg, getKillRegState(isKillSrc));
269 */
270  if (copyPhysVectorReg(mbb, mbbi, dl, destReg, srcReg, killSrc)) {
271  return;
272  }
273 
274  if (TCE::R1RegsRegClass.contains(destReg, srcReg)) {
275  BuildMI(mbb, mbbi, dl, get(TCE::MOVI1rr), destReg)
276  .addReg(srcReg, getKillRegState(killSrc));
277  } else if (TCE::R32IRegsRegClass.contains(destReg, srcReg)) {
278  BuildMI(mbb, mbbi, dl, get(TCE::MOVI32rr), destReg)
279  .addReg(srcReg, getKillRegState(killSrc));
280  } else if (TCE::R64RegsRegClass.contains(destReg, srcReg)) {
281  BuildMI(mbb, mbbi, dl, get(TCE::MOV64ss), destReg)
282  .addReg(srcReg, getKillRegState(killSrc));
283  } else if (TCE::FPRegsRegClass.contains(destReg, srcReg)) {
284  BuildMI(mbb, mbbi, dl, get(TCE::MOVff), destReg)
285  .addReg(srcReg, getKillRegState(killSrc));
286  } else if (TCE::HFPRegsRegClass.contains(destReg, srcReg)) {
287  BuildMI(mbb, mbbi, dl, get(TCE::MOVhh), destReg)
288  .addReg(srcReg, getKillRegState(killSrc));
289  } else if (TCE::R1RegsRegClass.contains(destReg) &&
290  TCE::R32IRegsRegClass.contains(srcReg)) {
291  BuildMI(mbb, mbbi, dl, get(TCE::MOVI32I1rr), destReg)
292  .addReg(srcReg, getKillRegState(killSrc));
293  } else if (TCE::R1RegsRegClass.contains(srcReg) &&
294  TCE::R32IRegsRegClass.contains(destReg)) {
295  BuildMI(mbb, mbbi, dl, get(TCE::MOVI1I32rr), destReg)
296  .addReg(srcReg, getKillRegState(killSrc));
297  } else if (TCE::GuardRegsRegClass.contains(destReg, srcReg)) {
298  BuildMI(mbb, mbbi, dl, get(TCE::MOVGrr), destReg)
299  .addReg(srcReg, getKillRegState(killSrc));
300  } else if (TCE::GuardRegsRegClass.contains(srcReg) &&
301  TCE::R32IRegsRegClass.contains(destReg)) {
302  BuildMI(mbb, mbbi, dl, get(TCE::MOVGI32rr), destReg)
303  .addReg(srcReg, getKillRegState(killSrc));
304  } else if (TCE::R32IRegsRegClass.contains(srcReg) &&
305  TCE::GuardRegsRegClass.contains(destReg)) {
306  BuildMI(mbb, mbbi, dl, get(TCE::MOVI32Grr), destReg)
307  .addReg(srcReg, getKillRegState(killSrc));
308  } else if (TCE::GuardRegsRegClass.contains(srcReg) &&
309  TCE::R1RegsRegClass.contains(destReg)) {
310  BuildMI(mbb, mbbi, dl, get(TCE::MOVGI1rr), destReg)
311  .addReg(srcReg, getKillRegState(killSrc));
312  } else if (TCE::R1RegsRegClass.contains(srcReg) &&
313  TCE::GuardRegsRegClass.contains(destReg)) {
314  BuildMI(mbb, mbbi, dl, get(TCE::MOVI1Grr), destReg)
315  .addReg(srcReg, getKillRegState(killSrc));
316  } else {
317  assert(
318  false && "TCERegisterInfo::copyPhysReg(): Can't copy register");
319 
320  }
321 }

References assert, and copyPhysVectorReg().

Here is the call graph for this function:

◆ copyPhysVectorReg()

bool llvm::TCEInstrInfo::copyPhysVectorReg ( MachineBasicBlock &  mbb,
MachineBasicBlock::iterator  mbbi,
const DebugLoc &  DL,
MCRegister  destReg,
MCRegister  srcReg,
bool  killSrc 
) const
private

Referenced by copyPhysReg().

◆ CreateTargetScheduleState()

DFAPacketizer * TCEInstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo &  STI) const
overridevirtual

Definition at line 726 of file TCEInstrInfo.cc.

727  {
728  const InstrItineraryData *II = STI.getInstrItineraryData();
729  DFAPacketizer *dfa =
730  static_cast<const TCESubtarget &>(STI).createDFAPacketizer(II);
731  assert(dfa != nullptr);
732  return dfa;
733 }

References assert.

◆ getInstrItineraryData()

const InstrItineraryData* llvm::TCEInstrInfo::getInstrItineraryData ( ) const
inline

Definition at line 63 of file TCEInstrInfo.hh.

63  {
64  return &InstrItins;
65  }

References InstrItins.

◆ getMatchingCondBranchOpcode()

int TCEInstrInfo::getMatchingCondBranchOpcode ( int  Opc,
bool  inverted 
) const
private

Definition at line 669 of file TCEInstrInfo.cc.

669  {
670 
671  if (!inv) {
672  return plugin_->getTruePredicateOpcode(opc);
673  } else {
674  return plugin_->getFalsePredicateOpcode(opc);
675  }
676 }

References llvm::TCETargetMachinePlugin::getFalsePredicateOpcode(), llvm::TCETargetMachinePlugin::getTruePredicateOpcode(), and plugin_.

Referenced by isPredicable(), and PredicateInstruction().

Here is the call graph for this function:

◆ getPointerAdjustment()

std::tuple< int, int > TCEInstrInfo::getPointerAdjustment ( int  offset) const

Return opcode for pointer adjustment and new offset.

Returns opcode available or suitable for pointer adjustment with constant offset value.

Parameters
offsetThe offset for the pointer.
Returns
(opcode, new offset) tuple.

Definition at line 721 of file TCEInstrInfo.cc.

721  {
722  return plugin_->getPointerAdjustment(offset);
723 }

References llvm::TCETargetMachinePlugin::getPointerAdjustment(), and plugin_.

Referenced by llvm::TCEFrameLowering::eliminateCallFramePseudoInstr(), llvm::TCERegisterInfo::eliminateFrameIndex(), and llvm::TCEFrameLowering::emitPrologue().

Here is the call graph for this function:

◆ getRegisterInfo()

virtual const TargetRegisterInfo& llvm::TCEInstrInfo::getRegisterInfo ( ) const
inlinevirtual

Definition at line 67 of file TCEInstrInfo.hh.

67  {
68  return ri_;
69  }

References ri_.

◆ insertBranch()

unsigned TCEInstrInfo::insertBranch ( MachineBasicBlock &  mbb,
MachineBasicBlock *  tbb,
MachineBasicBlock *  fbb,
ArrayRef< MachineOperand >  cond,
const DebugLoc &  dl,
int *  BytesAdded = nullptr 
) const
overridevirtual

Inserts a branch instruction or brach instructions into llvm MBB.

If the MBB already has an unconditional branch at end, does nothing.

Parameters
mbbwhere to insert the branch instructions.
tbbjump target basic block
fbbfalse condition jump target, if insertin 2 branches
Returns
number of branch instructions inserted

Definition at line 97 of file TCEInstrInfo.cc.

103  {
104  assert(cond.size() == 0 || cond.size() == 2 || cond.size() == 3);
105 
106  if (mbb.size() != 0) {
107  // already has a uncond branch, no need for another.
108  // asserts to make sure it's to same BB in order to not create
109  // broken code.
110  if (mbb.back().getOpcode() == TCE::TCEBR ||
111  mbb.back().getOpcode() == TCE::TCEBRIND) {
112  assert(cond.size() == 0);
113  return 0;
114  }
115  if (cond.size() != 0) {
116  assert (mbb.back().getOpcode() != TCE::TCEBRCOND && "c branch!");
117  assert (mbb.back().getOpcode() != TCE::TCEBRICOND && "ic branch!");
118  assert (mbb.back().getOpcode() != TCE::TCEBR && "has branch!(1)");
119  } else {
120  assert (mbb.back().getOpcode() != TCE::TCEBR && "has branch(2)!");
121  }
122 
123  }
124 
125  if (fbb == 0) {
126  if (cond.empty()) {
127  // Can only insert uncond branches so far.
128  BuildMI(&mbb, dl, get(TCE::TCEBR)).addMBB(tbb);
129  return 1;
130  } else {
131  if (cond.size() == 2 && cond[1].getImm() == false) {
132  // false jump
133  BuildMI(&mbb, dl, get(TCE::TCEBRICOND)).
134  addReg(cond[0].getReg()).addMBB(tbb);
135  return 1;
136  } else if (cond.size() == 2 && cond[1].getImm() == true) {
137  BuildMI(&mbb, dl, get(TCE::TCEBRCOND)).addReg(cond[0].getReg())
138  .addMBB(tbb);
139  return 1;
140  } else {
141  insertCCBranch(mbb, *tbb, cond, dl);
142  return 1;
143  }
144  }
145  }
146 
147  assert(
148  !cond.empty() &&
149  "Two jumps need a condition"); // not allowed to have conditional
150  // jump because we have an fbb
151 
152  if (cond.size() == 2 && cond[1].getImm() == false) {
153  BuildMI(&mbb, dl, get(TCE::TCEBRICOND)).
154  addReg(cond[0].getReg()).addMBB(tbb);
155  } else if (cond.size() == 1 ||
156  (cond.size() == 2 && cond[1].getImm() == true)) {
157  BuildMI(&mbb, dl, get(TCE::TCEBRCOND)).
158  addReg(cond[0].getReg()).addMBB(tbb);
159  } else {
160  insertCCBranch(mbb, *tbb, cond, dl);
161  }
162  BuildMI(&mbb, dl, get(TCE::TCEBR)).addMBB(fbb);
163 
164  return 2;
165 }

References assert, and insertCCBranch().

Here is the call graph for this function:

◆ insertCCBranch()

virtual void llvm::TCEInstrInfo::insertCCBranch ( MachineBasicBlock &  mbb,
MachineBasicBlock &  tbb,
ArrayRef< MachineOperand >  cond,
const DebugLoc &  dl 
) const
virtual

Referenced by insertBranch().

◆ isPredicable()

bool TCEInstrInfo::isPredicable ( const MachineInstr &  MI) const
overridevirtual

Definition at line 576 of file TCEInstrInfo.cc.

576  {
577  const MachineInstr* mi = &mi_ref;
578  if (mi->getOpcode() == TCE::COPY) {
579  return false;
580  }
581 
582  // TODO: why is RETL not predicable?
583  if (mi->getOpcode() == TCE::RETL) {
584  return false;
585  }
586 
587  if (isPredicated(*mi)) {
588  return false;
589  }
590 
591  if (getMatchingCondBranchOpcode(mi->getOpcode(),false) == -1) {
592  return false;
593  }
594 
595  for (int oper = mi->getNumOperands() - 1; oper >= 0; --oper) {
596  MachineOperand mo = mi->getOperand(oper);
597 
598  if ((mo.isReg() && !mo.isUse() && !mo.isImplicit())) {
599  continue;
600  }
601 
602  // TODO: support operand changing for fp imms etc.!
603  if (!mo.isReg() && !mo.isImm()) {
604  return false;
605  }
606  }
607  return true;
608 }

References getMatchingCondBranchOpcode(), and isPredicated().

Referenced by PredicateInstruction().

Here is the call graph for this function:

◆ isPredicated()

bool TCEInstrInfo::isPredicated ( const MachineInstr &  MI) const
overridevirtual

Definition at line 559 of file TCEInstrInfo.cc.

559  {
560  const MachineInstr* mi = &mi_ref;
561  // TODO: should be conditional move here..
562  if (mi->getOpcode() == TCE::RETL) {
563  return false;
564  }
565 
566  // KILL is not a predicated instruction.
567  if (mi->getOpcode() == TCE::KILL) {
568  return false;
569  }
570 
571  TCEString opName = plugin_->operationName(mi->getOpcode());
572  return opName[0] == '?' || opName[0] == '!';
573 }

References llvm::TCETargetMachinePlugin::operationName(), and plugin_.

Referenced by isPredicable().

Here is the call graph for this function:

◆ isProfitableToIfCvt() [1/2]

bool TCEInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
overridevirtual

Definition at line 699 of file TCEInstrInfo.cc.

702  {
703  return true;
704 }

◆ isProfitableToIfCvt() [2/2]

bool TCEInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock &  FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
BranchProbability  Probability 
) const
overridevirtual

Definition at line 709 of file TCEInstrInfo.cc.

715  {
716  return true;
717 }

◆ loadRegFromStackSlot() [1/2]

virtual void llvm::TCEInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  mbb,
MachineBasicBlock::iterator  mbbi,
Register  destReg,
int  frameIndex,
const TargetRegisterClass *  rc,
const TargetRegisterInfo *   
) const
inlineoverridevirtual

Definition at line 108 of file TCEInstrInfo.hh.

112  {
113  loadRegFromStackSlot(mbb, mbbi, destReg, frameIndex, rc);
114  }

References loadRegFromStackSlot().

Here is the call graph for this function:

◆ loadRegFromStackSlot() [2/2]

void TCEInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  mbb,
MachineBasicBlock::iterator  mbbi,
unsigned  destReg,
int  frameIndex,
const TargetRegisterClass *  rc 
) const
virtual

Definition at line 229 of file TCEInstrInfo.cc.

231  {
232  DebugLoc DL;
233 
234  if (I != MBB.end()) DL = I->getDebugLoc();
235  BuildMI(MBB, I, DL, get(plugin_->getLoad(RC)), DestReg).addFrameIndex(FI)
236  .addImm(0);
237 
238  LLVMContext& context = MBB.getParent()->getFunction().getContext();
239  llvm::Metadata* md = llvm::MDString::get(context, "AA_CATEGORY_STACK_SLOT");
240  MDNode* mdNode =
241  MDNode::get(context, llvm::ArrayRef<llvm::Metadata*>(&md, 1));
242  MachineOperand metaDataOperand = MachineOperand::CreateMetadata(mdNode);
243  I--; // buildmi moves the iterator to next ins, point to the created one.
244  I->addOperand(metaDataOperand);
245 }

References llvm::TCETargetMachinePlugin::getLoad(), and plugin_.

Referenced by loadRegFromStackSlot().

Here is the call graph for this function:

◆ PredicateInstruction()

bool TCEInstrInfo::PredicateInstruction ( MachineInstr &  mi,
ArrayRef< MachineOperand >  cond 
) const
overridevirtual

Definition at line 612 of file TCEInstrInfo.cc.

615  {
616 
617  MachineInstr *mi = &mi_ref;
618 
619  int opc = mi->getOpcode();
620 
621  assert (isPredicable(*mi) && "Expected predicable instruction");
622 
623  bool invertJump = (cond.size() >1 && cond[1].isImm() &&
624  (cond[1].getImm() == 0));
625 
626  mi->setDesc(get(getMatchingCondBranchOpcode(opc, invertJump)));
627  //
628  // This assumes that the predicate is always the first operand
629  // in the set of inputs.
630  //
631  mi->addOperand(mi->getOperand(mi->getNumOperands()-1));
632  int oper;
633  // why -3 in hexagon?
634  for (oper = mi->getNumOperands() - 2; oper >= 0; --oper) {
635  MachineOperand mo = mi->getOperand(oper);
636  // todo: why this break in hexagon?
637  if ((mo.isReg() && !mo.isUse() && !mo.isImplicit())) {
638  break;
639  }
640 
641  if (mo.isReg()) {
642  mi->getOperand(oper+1).ChangeToRegister(mo.getReg(), mo.isDef(),
643  mo.isImplicit(), mo.isKill(),
644  mo.isDead(), mo.isUndef(),
645  mo.isDebug());
646  } else if (mo.isImm()) {
647  mi->getOperand(oper+1).ChangeToImmediate(mo.getImm());
648  } else if (mo.isFPImm()) {
649  mi->getOperand(oper+1).ChangeToFPImmediate(mo.getFPImm());
650  } else if (mo.isGlobal()) {
651  // TODO: what to do here?
652  llvm_unreachable("Unexpected operand type");
653  mi->getOperand(oper+1).ChangeToImmediate(mo.getImm());
654  } else {
655  llvm_unreachable("Unexpected operand type");
656  }
657  }
658 
659  MachineOperand PredMO = cond[0];
660  mi->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
661  PredMO.isImplicit(), PredMO.isKill(),
662  PredMO.isDead(), PredMO.isUndef(),
663  PredMO.isDebug());
664 
665  return true;
666 }

References assert, getMatchingCondBranchOpcode(), and isPredicable().

Here is the call graph for this function:

◆ removeBranch()

unsigned TCEInstrInfo::removeBranch ( MachineBasicBlock &  mbb,
int *  BytesRemoved = nullptr 
) const
override

Removes branch or branches form end of llvm MachineBasicBlock

Parameters
mbbwhere to remove the branches from
Returns
number of braches removed

Definition at line 174 of file TCEInstrInfo.cc.

175  {
176  int j = 0;
177  MachineBasicBlock::iterator i = mbb.end();
178  while (i != mbb.begin()) {
179  i--;
180  int opc = i->getOpcode();
181  if (i->getDesc().isBranch()) {
182  i->eraseFromParent();
183  i = mbb.end(); // not optimal, but we will not miss any
184  // instruction
185  j++;
186  }
187  }
188  return j;
189 }

◆ reverseBranchCondition()

bool TCEInstrInfo::reverseBranchCondition ( llvm::SmallVectorImpl< llvm::MachineOperand > &  cond) const
overridevirtual

Definition at line 331 of file TCEInstrInfo.cc.

332  {
333  assert(cond.size() != 0);
334 
335  // from true to false
336  if (cond.size() == 1) {
337  cond.push_back(MachineOperand::CreateImm(false));
338  return false;
339  } else if (cond.size() == 2) {
340  // from false to true
341  if (cond[1].getImm() == false) {
342  cond[1].setImm(true);
343  } else {
344  // from true to false
345  assert(cond[1].getImm() == true);
346  cond[1].setImm(false);
347  }
348  return false;
349  } else if (cond.size() == 3) {
350  switch (cond[2].getImm()) {
351  case 2:
352  // eq -> ne
353  cond[2].setImm(3);
354  return false;
355  case 3:
356  // ne -> eq
357  cond[2].setImm(2);
358  return false;
359  case 4:
360  // gt -> le
361  cond[2].setImm(5);
362  return false;
363  case 5:
364  // le -> gt
365  cond[2].setImm(4);
366  return false;
367  case 6:
368  // ltu -> geu
369  cond[2].setImm(7);
370  return false;
371  case 7:
372  // geu -> ltu
373  cond[2].setImm(6);
374  return false;
375  case 14:
376  // lt -> ge
377  cond[2].setImm(16);
378  return false;
379  case 15:
380  // ltu -> geu
381  cond[2].setImm(17);
382  return false;
383  case 16:
384  // ge -> lt
385  cond[2].setImm(14);
386  return false;
387  case 17:
388  // geu -> ltu
389  cond[2].setImm(15);
390  return false;
391  // case 100+: register-immediate versions of branch ops
392  case 102:
393  // eg -> ne
394  cond[2].setImm(103);
395  return false;
396  case 103:
397  // ne -> eq
398  cond[2].setImm(102);
399  return false;
400  case 104:
401  // gt -> le
402  cond[2].setImm(105);
403  return false;
404  case 105:
405  // le -> gt
406  cond[2].setImm(104);
407  return false;
408  case 106:
409  // ltu -> geu
410  cond[2].setImm(107);
411  return false;
412  case 107:
413  // geu -> ltu
414  cond[2].setImm(106);
415  return false;
416  case 114:
417  // lt -> ge
418  cond[2].setImm(116);
419  return false;
420  case 115:
421  // ltu -> geu
422  cond[2].setImm(117);
423  return false;
424  case 116:
425  // ge -> lt
426  cond[2].setImm(114);
427  return false;
428  case 117:
429  // geu -> ltu
430  cond[2].setImm(115);
431  return false;
432  default:
433  return true;
434  }
435  }
436  return true;
437 }

References assert.

◆ storeRegToStackSlot() [1/2]

virtual void llvm::TCEInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  mbb,
MachineBasicBlock::iterator  mbbi,
Register  srcReg,
bool  isKill,
int  frameIndex,
const TargetRegisterClass *  rc,
const TargetRegisterInfo *   
) const
inlineoverridevirtual

Definition at line 91 of file TCEInstrInfo.hh.

95  {
96  storeRegToStackSlot(mbb, mbbi, srcReg, isKill, frameIndex, rc);
97  }

References storeRegToStackSlot().

Here is the call graph for this function:

◆ storeRegToStackSlot() [2/2]

void TCEInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  mbb,
MachineBasicBlock::iterator  mbbi,
unsigned  srcReg,
bool  isKill,
int  frameIndex,
const TargetRegisterClass *  rc 
) const
virtual

Definition at line 209 of file TCEInstrInfo.cc.

211  {
212  DebugLoc DL;
213 
214  if (I != MBB.end()) DL = I->getDebugLoc();
215 
216  BuildMI(MBB, I, DL, get(plugin_->getStore(RC))).addFrameIndex(FI).addImm(0)
217  .addReg(SrcReg, getKillRegState(isKill));
218 
219  LLVMContext& context = MBB.getParent()->getFunction().getContext();
220  llvm::Metadata* md = llvm::MDString::get(context, "AA_CATEGORY_STACK_SLOT");
221  MDNode* mdNode =
222  MDNode::get(context, llvm::ArrayRef<llvm::Metadata*>(&md, 1));
223  MachineOperand metaDataOperand = MachineOperand::CreateMetadata(mdNode);
224  I--; // buildmi moves the iterator to next ins, point to the created one.
225  I->addOperand(metaDataOperand);
226 }

References llvm::TCETargetMachinePlugin::getStore(), and plugin_.

Referenced by storeRegToStackSlot().

Here is the call graph for this function:

◆ SubsumesPredicate()

virtual bool llvm::TCEInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand >  Pred1,
ArrayRef< MachineOperand >  Pred2 
) const
inlineoverridevirtual

Definition at line 151 of file TCEInstrInfo.hh.

153  {
154  return false;
155  }

Member Data Documentation

◆ InstrItins

InstrItineraryData llvm::TCEInstrInfo::InstrItins
private

Definition at line 188 of file TCEInstrInfo.hh.

Referenced by getInstrItineraryData().

◆ plugin_

const TCETargetMachinePlugin* llvm::TCEInstrInfo::plugin_
private

Definition at line 193 of file TCEInstrInfo.hh.

Referenced by analyzeBranch(), getMatchingCondBranchOpcode(), getPointerAdjustment(), isPredicated(), loadRegFromStackSlot(), and storeRegToStackSlot().

◆ ri_

const TCERegisterInfo llvm::TCEInstrInfo::ri_
private

Definition at line 192 of file TCEInstrInfo.hh.

Referenced by ClobbersPredicate(), and getRegisterInfo().

The documentation for this class was generated from the following files:
llvm::TCETargetMachinePlugin::getStore
virtual int getStore(const TargetRegisterClass *rc) const =0
llvm::TCEInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const override
Definition: TCEInstrInfo.cc:559
llvm::TCESubtarget
Definition: TCESubtarget.hh:56
llvm::TCEInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, unsigned destReg, int frameIndex, const TargetRegisterClass *rc) const
Definition: TCEInstrInfo.cc:229
llvm::TCETargetMachinePlugin::analyzeCCBranch
virtual bool analyzeCCBranch(llvm::MachineInstr &i, llvm::SmallVectorImpl< llvm::MachineOperand > &cond) const
Definition: TCETargetMachinePlugin.hh:238
llvm::TCEInstrInfo::isPredicable
virtual bool isPredicable(const MachineInstr &MI) const override
Definition: TCEInstrInfo.cc:576
assert
#define assert(condition)
Definition: Application.hh:86
llvm::TCETargetMachinePlugin::getFalsePredicateOpcode
virtual int getFalsePredicateOpcode(unsigned opc) const =0
llvm::TCEInstrInfo::insertCCBranch
virtual void insertCCBranch(MachineBasicBlock &mbb, MachineBasicBlock &tbb, ArrayRef< MachineOperand > cond, const DebugLoc &dl) const
llvm::TCEInstrInfo::plugin_
const TCETargetMachinePlugin * plugin_
Definition: TCEInstrInfo.hh:193
llvm::TCETargetMachinePlugin::getLoad
virtual int getLoad(const TargetRegisterClass *rc) const =0
llvm::TCEInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, unsigned srcReg, bool isKill, int frameIndex, const TargetRegisterClass *rc) const
Definition: TCEInstrInfo.cc:209
llvm::TCETargetMachinePlugin::getPointerAdjustment
virtual std::tuple< int, int > getPointerAdjustment(int offset) const =0
llvm::TCEInstrInfo::copyPhysVectorReg
bool copyPhysVectorReg(MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, const DebugLoc &DL, MCRegister destReg, MCRegister srcReg, bool killSrc) const
llvm::TCEInstrInfo::getMatchingCondBranchOpcode
int getMatchingCondBranchOpcode(int Opc, bool inverted) const
Definition: TCEInstrInfo.cc:669
llvm::TCEInstrInfo::InstrItins
InstrItineraryData InstrItins
Definition: TCEInstrInfo.hh:188
llvm::TCETargetMachinePlugin::getTruePredicateOpcode
virtual int getTruePredicateOpcode(unsigned opc) const =0
TCEString
Definition: TCEString.hh:53
llvm::TCEInstrInfo::ri_
const TCERegisterInfo ri_
Definition: TCEInstrInfo.hh:192
llvm::TCETargetMachinePlugin::operationName
virtual std::string operationName(unsigned opc) const =0
Returns operation name corresponding to llvm target opcode.
Generated by   doxygen 1.8.17