OpenASIP  2.0
Classes | Enumerations | Functions
ProGe Namespace Reference

Classes

class  BaseNetlistBlock
 
class  BlockSourceCopier
 
class  CUOpcodeGenerator
 
class  GeneratableFUNetlistBlock
 
class  GlobalPackage
 
class  ICDecoderGeneratorPlugin
 
class  IGenerationPhases
 
class  InBitPort
 Convenience class for input bit ports. More...
 
class  InPort
 Convenience class for input ports. More...
 
class  InverterBlock
 
class  LoopBufferBlock
 
class  MemoryBusInterface
 
class  MicroCodeGenerator
 
class  Netlist
 
class  NetlistBlock
 
class  NetlistBlockNameComparator
 
class  NetlistGenerator
 
class  NetlistPort
 
class  NetlistPortGroup
 
class  NetlistTools
 
class  NetlistVisualization
 
class  NetlistWriter
 
class  OutBitPort
 Convenience class for output bit ports. More...
 
class  OutPort
 Convenience class for output ports. More...
 
class  Parameter
 
class  PortConnectionProperty
 
class  PortFactory
 
class  ProcessorGenerator
 
class  ProcessorWrapperBlock
 
class  ProGeContext
 
class  ProGeUI
 
class  RV32MicroCodeGenerator
 
class  Signal
 
class  SignalGroup
 
class  SinglePortByteMaskSSRAMBlock
 
class  SinglePortSSRAMBlock
 
class  StaticSignal
 
class  TestBenchBlock
 
class  VerilogNetlistWriter
 
class  VHDLNetlistWriter
 
class  VirtualNetlistBlock
 

Enumerations

enum  HDL { VHDL =0, Verilog }
 HDLs supported by ProGe. More...
 
enum  DataType { BIT, BIT_VECTOR }
 Data types of hardware ports. More...
 
enum  Direction { IN, OUT, BIDIR }
 Direction of the port. More...
 
enum  SignalGroupType {
  SignalGroupType::UNDEFINED = 0, SignalGroupType::INTERNAL, SignalGroupType::USERDEFINED, SignalGroupType::INSTRUCTION_LINE,
  SignalGroupType::BURST_INSTRUCTION, SignalGroupType::BITMASKED_SRAM_PORT, SignalGroupType::BITMASKED_ROM_PORT, SignalGroupType::BYTEMASKED_SRAM_PORT
}
 
enum  SignalType {
  SignalType::UNDEFINED = 0, SignalType::OPEN, SignalType::INTERNAL, SignalType::USERDEFINED,
  SignalType::CLOCK, SignalType::RESET, SignalType::ADDRESS, SignalType::INSTRUCTIONWORD,
  SignalType::FETCHBLOCK, SignalType::READ_REQUEST, SignalType::BURST_READ_REQUEST, SignalType::READ_REQUEST_READY,
  SignalType::BURST_READ_REQUEST_READY, SignalType::WRITE_REQUEST, SignalType::READ_WRITE_REQUEST, SignalType::WRITEMODE,
  SignalType::ENABLE, SignalType::BUSY, SignalType::STALL = BUSY, SignalType::GLOCK_REQUEST,
  SignalType::GLOCK, SignalType::INVALIDATE_CACHE, SignalType::READ_DATA, SignalType::WRITE_DATA,
  SignalType::WRITE_BITMASK, SignalType::CORE_HALT_STATUS, SignalType::AVALID, SignalType::AREADY,
  SignalType::AADDR, SignalType::AWREN, SignalType::ASTRB, SignalType::RVALID,
  SignalType::RREADY, SignalType::RDATA, SignalType::ADATA
}
 
enum  ActiveState { ActiveState::HIGH = 0, ActiveState::LOW }
 

Functions

std::set< SignalTypesignalGroupDefinition (SignalGroupType type)
 

Enumeration Type Documentation

◆ ActiveState

enum ProGe::ActiveState
strong
Enumerator
HIGH 
LOW 

Definition at line 118 of file SignalTypes.hh.

118  {
119  HIGH = 0,
120  LOW
121 };

◆ DataType

Data types of hardware ports.

Enumerator
BIT 

One bit.

BIT_VECTOR 

Several bits.

Definition at line 46 of file ProGeTypes.hh.

46  {
47  BIT, ///< One bit.
48  BIT_VECTOR ///< Several bits.
49 };

◆ Direction

Direction of the port.

Enumerator
IN 

Input port.

OUT 

Output port.

BIDIR 

Bidirectional port.

Definition at line 52 of file ProGeTypes.hh.

52  {
53  IN, ///< Input port.
54  OUT, ///< Output port.
55  BIDIR ///< Bidirectional port.
56 };

◆ HDL

enum ProGe::HDL

HDLs supported by ProGe.

Enumerator
VHDL 

VHDL.

Verilog 

Verilog.

Definition at line 40 of file ProGeTypes.hh.

40  {
41  VHDL=0, ///< VHDL
42  Verilog ///< Verilog
43 };

◆ SignalGroupType

List of signal group types. See SignalGroupDefinition.hh for definitions of the group types.

Enumerator
UNDEFINED 
INTERNAL 

Signal group is internally defined custom signal.

USERDEFINED 

Signal group is externally defined custom signal.

INSTRUCTION_LINE 

Signal group type for serial TTA instruction bus.

BURST_INSTRUCTION 

Signal group type for burst TTA instruction bus.

BITMASKED_SRAM_PORT 

Signal group type for one port SRAM having read and write capability and bitmask for writing.

BITMASKED_ROM_PORT 

Signal group type for one port ROM.

BYTEMASKED_SRAM_PORT 

Signal group type for one port SRAM having read and write capability and bitmask for writing with separate address and data handshake.

Definition at line 43 of file SignalGroupTypes.hh.

43  {
44  UNDEFINED = 0,
45  /// Signal group is internally defined custom signal.
46  INTERNAL,
47  /// Signal group is externally defined custom signal.
49  /// Signal group type for serial TTA instruction bus.
51  /// Signal group type for burst TTA instruction bus.
53  /// Signal group type for one port SRAM having read and write capability
54  /// and bitmask for writing.
56  /// Signal group type for one port ROM.
58  /// Signal group type for one port SRAM having read and write capability
59  /// and bitmask for writing with separate address and data handshake.
61 };

◆ SignalType

enum ProGe::SignalType
strong

List of different types of signal. The types are also used as numerical IDs for connecting similiar NetlistPorts together.

Enumerator
UNDEFINED 

Signal does not have specified usage.

OPEN 

Signal is left to unconnected.

INTERNAL 

Signal is internally defined custom signal.

USERDEFINED 

Signal is externally defined custom signal.

CLOCK 

Clock signal.

RESET 

Reset signal.

ADDRESS 

Signal holds address.

INSTRUCTIONWORD 

Signal contains TTA (decompressed) instruction.

FETCHBLOCK 

Signal is TTA instruction block block containing (compressed) instruction.

READ_REQUEST 

Signal to make read request.

BURST_READ_REQUEST 

Signal to make burst read request.

READ_REQUEST_READY 

Signal to tell that requested data can be read.

BURST_READ_REQUEST_READY 

Signal to tell that part of burst-requested data can be read.

WRITE_REQUEST 

Signal to make write request.

READ_WRITE_REQUEST 

Signal to make either read or write request.

WRITEMODE 

Signal to choose mode for READ_WRITE_REQUEST or similar.

ENABLE 

Signal to enable or activate a device.

BUSY 

Signal telling that source device is not ready to handle a request.

STALL 

Signal to stopping destination device.

GLOCK_REQUEST 

TTA Global lock request signal.

GLOCK 

TTA Global lock signal.

INVALIDATE_CACHE 

Cache Invalidation signal.

READ_DATA 
WRITE_DATA 
WRITE_BITMASK 
CORE_HALT_STATUS 

Signal that tell if core is halted.

AVALID 

Signal types for memory interface with separate valid/ready in address/data.

AREADY 
AADDR 
AWREN 
ASTRB 
RVALID 
RREADY 
RDATA 
ADATA 

Definition at line 42 of file SignalTypes.hh.

42  {
43  /// Signal does not have specified usage.
44  UNDEFINED = 0,
45  /// Signal is left to unconnected.
46  OPEN,
47  /// Signal is internally defined custom signal.
48  INTERNAL,
49  /// Signal is externally defined custom signal.
51  /// Clock signal.
52  CLOCK,
53  /// Reset signal.
54  RESET,
55  /// Signal holds address.
56  ADDRESS,
57  /// Signal contains TTA (decompressed) instruction.
59  /// Signal is TTA instruction block block containing (compressed)
60  /// instruction.
61  FETCHBLOCK,
62  /// Signal to make read request.
64  /// Signal to make burst read request.
66  /// Signal to tell that requested data can be read.
68  /// Signal to tell that part of burst-requested data can be read.
70  /// Signal to make write request.
72  /// Signal to make either read or write request.
74  /// Signal to choose mode for READ_WRITE_REQUEST or similar.
75  WRITEMODE,
76  /// Signal to enable or activate a device.
77  ENABLE,
78  /// Signal telling that source device is not ready to handle a request.
79  BUSY,
80  /// Signal to stopping destination device.
81  STALL = BUSY,
82  /// TTA Global lock request signal.
84  /// TTA Global lock signal.
85  GLOCK,
86  /// Cache Invalidation signal.
88  READ_DATA,
89  WRITE_DATA,
91  /// Signal that tell if core is halted.
93 
94  /// Signal types for memory interface with separate
95  /// valid/ready in address/data
96  AVALID,
97  AREADY,
98  AADDR,
99  AWREN,
100  ASTRB,
101  RVALID,
102  RREADY,
103  RDATA,
104  ADATA
105 
106  //todo consider these:
107  //DATA
108  //DATA0..DATAn < for vectors, 0..n to point vector element
109  //VECTORDATA < alternative for vector, SignalID to point vector element
110  //INSTRUCTION_ADDRESS
111  //DATA_ADDRESS
112  //FU_OPCODE
113  //FU_TRIGGER or FU_TRIGGER_LOAD = WRITE_REQUEST = LOAD
114  //FU_DATA < Either for trigger, operand or result data. Determined by
115  // associated SignalGroupType
116 };

Function Documentation

◆ signalGroupDefinition()

std::set< SignalType > ProGe::signalGroupDefinition ( SignalGroupType  type)

Returns set of SignalTypes defined by SignalGroupType.

Definition at line 86 of file SignalGroupDefinitions.cc.

86  {
87  if (definitions.count(type)) {
88  return definitions.at(type);
89  } else {
90  return std::set<SignalType>();
91  }
92 }
ProGe::SignalType::AVALID
@ AVALID
Signal types for memory interface with separate valid/ready in address/data.
ProGe::SignalType::BURST_READ_REQUEST_READY
@ BURST_READ_REQUEST_READY
Signal to tell that part of burst-requested data can be read.
ProGe::SignalType::FETCHBLOCK
@ FETCHBLOCK
Signal is TTA instruction block block containing (compressed) instruction.
ProGe::SignalGroupType::BYTEMASKED_SRAM_PORT
@ BYTEMASKED_SRAM_PORT
Signal group type for one port SRAM having read and write capability and bitmask for writing with sep...
ProGe::Verilog
@ Verilog
Verilog.
Definition: ProGeTypes.hh:42
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
ProGe::SignalType::CORE_HALT_STATUS
@ CORE_HALT_STATUS
Signal that tell if core is halted.
ProGe::SignalGroupType::USERDEFINED
@ USERDEFINED
Signal group is externally defined custom signal.
ProGe::SignalType::WRITE_BITMASK
@ WRITE_BITMASK
ProGe::SignalType::RVALID
@ RVALID
ProGe::SignalGroupType::INTERNAL
@ INTERNAL
Signal group is internally defined custom signal.
ProGe::SignalType::RESET
@ RESET
Reset signal.
ProGe::SignalType::WRITE_DATA
@ WRITE_DATA
ProGe::SignalType::ASTRB
@ ASTRB
ProGe::SignalType::WRITE_REQUEST
@ WRITE_REQUEST
Signal to make write request.
ProGe::ActiveState::HIGH
@ HIGH
ProGe::BIDIR
@ BIDIR
Bidirectional port.
Definition: ProGeTypes.hh:55
ProGe::SignalType::AREADY
@ AREADY
ProGe::SignalGroupType::INSTRUCTION_LINE
@ INSTRUCTION_LINE
Signal group type for serial TTA instruction bus.
ProGe::SignalType::WRITEMODE
@ WRITEMODE
Signal to choose mode for READ_WRITE_REQUEST or similar.
ProGe::ActiveState::LOW
@ LOW
ProGe::SignalType::GLOCK_REQUEST
@ GLOCK_REQUEST
TTA Global lock request signal.
ProGe::SignalType::STALL
@ STALL
Signal to stopping destination device.
ProGe::VHDL
@ VHDL
VHDL.
Definition: ProGeTypes.hh:41
ProGe::SignalType::GLOCK
@ GLOCK
TTA Global lock signal.
ProGe::SignalType::BURST_READ_REQUEST
@ BURST_READ_REQUEST
Signal to make burst read request.
ProGe::SignalType::AADDR
@ AADDR
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
ProGe::SignalType::ADDRESS
@ ADDRESS
Signal holds address.
ProGe::SignalType::RDATA
@ RDATA
ProGe::SignalType::OPEN
@ OPEN
Signal is left to unconnected.
ProGe::SignalType::CLOCK
@ CLOCK
Clock signal.
ProGe::SignalGroupType::BITMASKED_SRAM_PORT
@ BITMASKED_SRAM_PORT
Signal group type for one port SRAM having read and write capability and bitmask for writing.
ProGe::SignalType::READ_WRITE_REQUEST
@ READ_WRITE_REQUEST
Signal to make either read or write request.
ProGe::SignalGroupType::UNDEFINED
@ UNDEFINED
ProGe::SignalType::INSTRUCTIONWORD
@ INSTRUCTIONWORD
Signal contains TTA (decompressed) instruction.
ProGe::SignalType::READ_REQUEST_READY
@ READ_REQUEST_READY
Signal to tell that requested data can be read.
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
ProGe::SignalType::ADATA
@ ADATA
ProGe::SignalType::INVALIDATE_CACHE
@ INVALIDATE_CACHE
Cache Invalidation signal.
ProGe::SignalType::READ_REQUEST
@ READ_REQUEST
Signal to make read request.
ProGe::SignalType::READ_DATA
@ READ_DATA
ProGe::SignalType::AWREN
@ AWREN
ProGe::SignalType::BUSY
@ BUSY
Signal telling that source device is not ready to handle a request.
ProGe::SignalGroupType::BITMASKED_ROM_PORT
@ BITMASKED_ROM_PORT
Signal group type for one port ROM.
ProGe::SignalGroupType::BURST_INSTRUCTION
@ BURST_INSTRUCTION
Signal group type for burst TTA instruction bus.
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
ProGe::SignalType::RREADY
@ RREADY
ProGe::SignalType::ENABLE
@ ENABLE
Signal to enable or activate a device.