Questions related to memory accessing.
Big endian. At the moment, endianness cannot be customized.
The memory acessing operations in the base operation set (ldq, ldh, ldw, ldd, stq, sth, stw, and ldd) are aligned with their size. Operations stq/ldq are for accessing single minimum addressable units (MAU, usually bytes), thus their alignment is 1 MAU, for sth/ldh it is 2 MAUs, and for stw/ldw it is 4 MAUs. Thus, one cannot access, for example, a 4 MAU word at address 3.
Double precision floating point word operations std/ldd which access 64-bit words are aligned at 8-byte addresses. Thus, if your memory is addressed in 16-bit units, double words can be stored at addresses divisible by 4, if memory is byte-addressed, then addresses must be divisible by 8, and so on.
The default GCU assumes that instruction memory is intruction addressable. In other words the instruction word must fit in the MAU of the instruction memory. This way the next instruction can be referenced by incrementing the current memory address by one.
How to interface the instruction memory with an actual memory chip is out of scope in TCE because there are too many different platforms and chips and possibilities. But as an advantage this gives the user free hands to implement almost any kind of memory hierarchy the user wants. Most probably you must implement a memory adapter to bind the memory chip and the TTA processor interfaces together.
The heap (allocated with 'malloc' in C or 'new' in C++) and stack grow towards each other. Stack growes from the end of the data address space towards the beginning of the address space, while heap grows towards the end of the address space starting from the end of the global data area.
Thus, the correct way to increase the space for heap/stack is to increase the size of your data memory address space in the ADF.
Pekka Jääskeläinen 2010-05-28