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1 Memory Related
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TTA Codesign Environment User
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3 Automatic Design Space
Contents
7
FREQUENTLY ASKED QUESTIONS
Subsections
1
Memory Related
1
What is the endianness of the TTA processors designed with TCE?
2
What is the alignment of words when reading/writing memory?
3
Load Store Unit
4
Instruction Memory
5
Stack and Heap
2
Processor Generator
1
Warning: Processor Generator failed to generate a test bench
2
Warning: Opcode defined in HDB for operation ...
Pekka Jääskeläinen 2010-05-28