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1 TCE Tour
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TTA Codesign Environment User
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3 Notes About the
Contents
3
TUTORIALS AND HOW-TOS
Subsections
1
TCE Tour
1
The Sample Application
2
Starting Point Processor Architecture
3
Evaluating the Starting Point Architecture
4
Accelerating the Algorithm
1
Evaluating Custom Operation Candidates
2
Finding the Bottlenecks
5
Analyzing the Custom Operation
6
Creating the Custom Operation
1
Using Operation Set Editor (OSEd) to add the operation data.
2
Adding the new operations.
3
Defining the simulation behaviour of the operations
4
Compiling operation behavior.
5
Adding a Customized Function Unit to the Architecture.
7
Use the custom operation in C code.
8
Adding an implementation of the FU to the hardware database (HDB).
9
Generating the Final Products
1
Select Function Unit Implementations
2
Generate the VHDL for the processor using Processor Generator (ProGe).
3
Generate instruction memory bit image using Program Image Generator.
4
Simulation and verification
10
Increasing performance by adding resources
1
Transport buses.
2
Register files.
3
Function units.
11
Final Words
2
From C to VHDL as Quickly as Possible
3
Hello TTA World!
4
Streaming I/O
1
Streaming I/O function units
5
Implementing Programs in Parallel Assembly Code
1
Preparations
2
Introduction to DCT
3
Introduction to TCE assembly
4
Implementing DCT on TCE assembly
1
Verifying the assembly program
6
Running TTA on FPGA
1
Simplest example: No data memory
1
Introduction
2
Application
3
Create TTA processor core and instruction image
4
Final steps to FPGA
2
Second example: Adding data memory
1
Create TTA processor core and binary images
2
Towards FPGA
3
More to test
7
Designing Floating-point Processors with TCE
1
Restrictions
2
Function Units
3
Benchmark results
4
Alternative bit widths
5
Processor Simulator and Floating Point Operations
8
Multi-TTA Designs
9
OpenCL Support
Pekka Jääskeläinen 2011-12-08