The main goal for the TTA Codesign Environment (TCE) is to provide a reliable and effective toolset for designing programmable application specific processors, and generate machine code for them from applications written in high-level languages.
In addition, TCE provides an extensible research platform for experimenting with new ideas for Transport Triggered Architectures (TTAs), retargetable ILP code generation, and application specific processor design methodology, among others.
The TCE design flow starts from an application described in a high level language (currently the C language). The LLVM compiler framework [llv08] is used to compile the application to 'bitcode', the intermediate representation of LLVM. The resulting bitcode is then compiled and scheduled to a particular TTA processor by TCE. Traditional compiler optimizations are done in LLVM before bitcode generation, so it is possible to utilize the same bitcode file when exploring different TTA processors for running an application.
The initial software development phase is intended to be separate from the actual codesign flow of TCE. That is, the program is expected to be implemented and tested natively (on a workstation PC) before ``porting'' it to the TTA/TCE platform. The porting includes ensuring that TTA/TCE runs the program correctly, and optimizing the hardware together with the software by modifying the resources and architecture of the processor to fit the application at hand - a process called hardware/software codesign.
The main phases in the design flow of TCE are illustrated in the following figures. Figure 2.1 depicts the initial inputs to TCE, Figure 2.2 the design space exploration phase, Figure 2.3 the processor configuration selection phase, Figure 2.4 the code generation and analysis phase, and Figure 2.5 the generation of the final outputs: the processor description and the program bit image.
Pekka Jääskeläinen 2011-12-08