Transport-triggered architectures (TTAs) [10] form a new class of architectures that differ from traditional operation-triggered architectures (OTAs) in the way they are programmed. Traditional OTAs are programmed by specifying operations. Each specified operation results in a few data-transports on the data path, e.g., an addition results in two data-transports of the operands to the ALU and one data-transport of the result from the ALU.

TTAs are programmed by specifying the data-transports, or moves, directly. All these moves are between internal registers. A TTA consists of a set of function units (FUs) and register units (RUs) connected by a fully or partially connected interconnection network. FUs provide functionality, RUs provide general purpose registers.

The register set is divided into general purpose, operand (O), trigger (T), and result (R) registers. General purpose registers (GPRs) are located in RUs and have the same function as the GPRs of OTAs. Operand registers are part of an FU; they are used to deliver operands. Similar to an operand register, a trigger register is also used to deliver an operand, however a move to a trigger register is also the signal for the FU that all operands have been delivered and the operation can start. After triggering, the operands are sent to a pipeline that does the operation. After the operation has completed the result is placed in the result register of the pipeline. With a move from a result register the result can be used for other operations or it can be stored in a GPR. Reading a result register is also the signal that the operation has ended and the result register can be used for the result of another operation on the same FU. As an example, the following move code is the translation of m[p]=m[q]+a, where p,q and a are stored in the GPRs rq, rp and ra:

This example shows that TTAs allow multiple moves per cycle; similar to very long instruction word (VLIW) computers, which allow multiple operations per cycle.

Besides doing operations, the architecture should also provide immediate operands, control flow, and conditional execution. Short immediates are stored in the source specifier of a move. Longer immediates are provided by reading parts of the instruction stream; the instruction register is visible in the architecture. When it is read, the immediate is taken from the instruction stream.

Control flow is done by simply writing a target address to the program counter. Reading the program counter can be used to save it for function calls. For the purpose of relative jumps, a special register is provided. Writing a displacement to this register causes a relative jump.

Conditional execution is done by means of guards. Compare FUs produce boolean results; each move can be guarded by a boolean expression of these booleans. Only when a guard expression evaluates true the guarded move takes place. Guards allow conditional execution of both data and flow control operations. Guards also incorporate multi-way branching.