News and updates Archive

September 4th, 2015: TCE 1.12 released

A new version of the toolset is now available for download.

See the release announcement for details and the change summary for details.

March 2nd, 2015: TCE 1.11 released

A new version of the toolset is now available for download.

See the release announcement

January 12th, 2015: new publications added

    • Yviquel Hervé, Sanchez Alexandre, Jääskeläinen Pekka, Takala Jarmo, Raulet Mickaël, Casseau Emmanuel:
      "Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs",
      in Journal of Signal Processing Systems, vol. 80, issue 1, July 2015 (download).
    • Kultala Heikki, Viitanen Timo, Jääskeläinen Pekka, Helkala Janne, Takala Jarmo:
      "Compiler Optimizations for Code Density of Variable Length Instructions",
      in 2014 IEEE Workshop on Signal Processing Systems (SiPS) (download).
    • Viitanen Timo, Kultala Heikki, Jääskeläinen Pekka, Takala Jarmo:
      "Heuristics for Greedy Transport Triggered Architecture Interconnect Exploration",
      in International Conference on Compilers, Architecture and Synthesis for Embedded Systems 2014 (CASES 14) (download).
    • Nyländen Teemu, Boutellier Jani, Nikunen Karri, Hannuksela Jari, Silvén Olli:
      "Low-power Reconfigurable Miniature Sensor Nodes for Condition Monitoring",
      in International Journal of Parallel Programming (download).
    • Hautala Ilkka, Boutellier Jani, Hannuksela Jari, Silvén Olli:
      "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering",
      in IEEE Transactions on Circuits and Systems for Video Technology (download).
    • Ghazi Amanullah, Boutellier Jani, Abdelaziz Mahmoud, Lu Xiaojia, Anttila Lauri, Cavallaro Joseph R, Bhattacharyya Shuvra S, Valkama Mikko, Juntti Markku:
      "Low Power Implementation of Digital Predistortion Filter on a Heterogeneous Application Specific Multiprocessor",
      in The 39th IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), Florence, Italy (download).

September 23rd, 2014: new publications and theses added

  • Jääskeläinen Pekka, Kultala Heikki, Viitanen Timo, Takala Jarmo:
    "Code Density and Energy Efficiency of Exposed Datapath Architectures",
    in Journal of Signal Processing Systems July 2014 (download).
  • Helkala Janne, Viitanen Timo, Kultala Heikki, Jääskeläinen Pekka, Takala Jarmo, Zetterman Tommi, Berg Heikki:
    "Variable Length Instruction Compression on Transport Triggered Architectures",
    in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014 (download).
  • Rister B., Jääskeläinen P., Silven O., Hannuksela J.:
    "Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding",
    in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
  • Yviquel H., Sanchez A., Jääskeläinen P., Takala J.:
    "Efficient software synthesis of dynamic dataflow programs",
    in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
  • Master's thesis of Janne Helkala:
    Variable Length Instruction Compression on Transport Triggered Architectures (June, 2014) (link)
  • Master's thesis of Mikko Järvelä:
    Vector Operation Support for Transport Triggered Architectures (June, 2014) (link)

September 5th, 2014: TCE 1.10 released

A new version of the toolset is now available for download.

See the release announcement for details.

February 27th, 2014: New research group name

The research group in Tampere University of Technology maintaining TCE was renamed from FlexASP to Customized Parallel Computing (CPC).

January 27th, 2014: TCE 1.9 released

A new version of the toolset is now available for download.

See the release announcement for details.

October 28th, 2013: new publications from Oulu added

A bunch of publications from University of Oulu that use TCE added.

October 17th, 2013: new publications added

New publications added:

  • Tomasz Patyk, David Guevorkian, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
    "Low-Power Application-Specific FFT Processor for LTE Applications",
    in SAMOS XIII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2013). (doi)
  • Heikki Kultala, Otto Esko, XianJun Jiao, Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Tommi Zetterman, Heikki Berg:
    "Turbo Decoding on Tailored OpenCL Processor",
    in IWCMC 2013: International Wireless Communications & Mobile Computing Conference (Cagliari, Italy, July 2013). (doi)
  • Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
    "Design Methodology for Offloading Software Executions to FPGA",
    in Journal of Signal Processing Systems, November 2011, vol. 65, issue 2. (doi)

June 18th, 2013: TCE 1.8 released

A new version of the toolset is now available for download.

See the release announcement for details.

January 21st, 2013: TCE 1.7 released

A new version of the toolset is now available for download.

See the release announcement for details.

Jan 9th, 2013: Master's thesis added: "Floating-Point Arithmetic in Transport Triggered Architectures"

A new Master's Thesis about floating-point support in TCE has been added to the publications section.

Nov 13th, 2012: A doctoral dissertation added: "From Parallel Programs to Customized Parallel Processors"

The doctoral dissertation of Pekka Jääskeläinen is now available in the publications section. The dissertation is about exploiting parallel programming languages in the parallel processor customization, and expanding the customization aspects to the multicore level.

June 7th, 2012: TCE 1.6 released

A new version of the toolset is now available for download.

This release adds support for LLVM 3.1, experimental Verilog backend for the Processor Generator, support for explicit access to multiple address spaces from C, a simplified C++ interface for accessing the simulation engine, automated generation of clustered-style TTA machines, experimental vector input and a bottom-up instruction scheduler. See the CHANGES file for a more thorough change listing.

May 12th, 2012: ASILOMAR '11 publication added

We presented a paper about our operation description format and compiler retargeting:

  • Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala
    "Operation Set Customization in Retargetable Compilers".
    Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 6-9 Nov 2011, Pacific Grove, California (IEEEexplore)

December 13th, 2011: TCE 1.5 released

A new version of the toolset is now available for download.

This release includes support for LLVM 3.0, experimental OpenCL C Embedded Profile support (in offline compilation/standalone mode), a light weight (debug output) printing library, support for calling custom operations in specific function units, generalizations to the architecture description format to allow using the instruction scheduler for operation triggered architectures (with a proof of concept for the Cell SPU), several code generator improvements and plenty of bug fixes. See the CHANGES file for a more thorough change listing.

November 4th, 2011: SoC'11 publications added

We presented two new papers related to TCE in the SoC 2011 conference:

  • Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala,
    "Customizable Datapath Integrated Lock Unit,"
  • Vladimír Guzma, Teemu Pitkänen, Jarmo Takala,
    "Effects of Loop Unrolling and Use of Instruction Buffer on Processor Energy Consumption,"
    in Proc. of International Symposium on System on Chip 2011, Tampere, Finland, October 31-November 2, 2011

October 19th, 2011: Portable OpenCL (pocl) released

The work started in early 2009 as an experiment to schedule OpenCL C kernels for standalone application-specific processors has been now generalized and released as a separate open source project called Portable OpenCL (pocl).

September 07th, 2011: SAMOS XI publications added

We presented two new papers in the SAMOS XI conference:

  • Pekka O. Jääskeläinen, Erno O. Salminen, Carlos S. de La Lama, Jarmo H. Takala, and Jose Ignacio Martinez,
    "TCEMC: A Co-Design Flow for Application-Specific Multicores".
  • Vladimír Guzma, Teemu Pitkänen, and Jarmo H. Takala,
    "Instruction Buffer with Limited Control Flow and Loop Nest Support".

August 18th, 2011: Publication added: ASIP Integration and Verification Flow

A new Master's Thesis about automatic ASIP integration and verification has been added to the publications.

In addition, a new Bachelor's Thesis, "Siirtoliipaistujen prosessorien käyttäminen FPGA-pohjaisissa järjestelmäpiireissä" (Utilizing Transport-Triggered Processors on FPGA-based System-on-Chip), written in Finnish, has been added to the publications.

July 7th, 2011: Publication added: OpenCL-based Design Methodology for Application-Specific Processors

A new journal paper, an extended version of our SAMOS 2010 paper that studied OpenCL in the context of ASIP design, has been published.

April 11th, 2011: TCE 1.4 released

A new version of the toolset is now available for download. Check the release announcement and the change log. Good luck with your new TTA designs!

--The TCE crew

Feb 28th, 2011: Publication added: Programmable and Scalable Architecture for Graphics Processing Units (extended version)

A new journal paper, an extended version of our SAMOS 2009 paper that studied TTA for GPU implementation, has been published.

Jan 19th, 2011: TCE 1.3 virtual machine image uploaded & slides for teaching

The virtual machine image for easy TCE experimentation has been updated to TCE 1.3. See the bottom of the download page for more info.

In the documentation section there are now some slide sets that can be useful for teaching or giving TCE tutorials.

Nov 10th, 2010: TCE 1.3 released

A new version of the toolset is now available for download. Check the release announcement and the change log. Good luck with your new TTA designs!

--The TCE crew