Publications
In case you use TCE in your research, please cite the following TCE paper in your publications. Although the paper is focused on FPGA soft core use while TCE is not limited only to FPGA implementation, it's currently the most up-to-date and decent "overview style" publication written of the TCE toolset.
- Otto Esko, Pekka Jääskeläinen, Pablo Huerta,
Carlos S. de La Lama, Jarmo Takala, Jose Ignacio Martinez,
“Customized Exposed Datapath Soft-Core Design Flow with Compiler Support”,
in 20th International Conference on Field Programmable Logic and Applications, Milano, Italy, August-September 2010, (PDF available)
@inproceedings{Esko:2010:CED:1933303.1933795,
author = {Esko, Otto and J\"a\"askel\"ainen, Pekka and Huerta, Pablo and de La Lama,
Carlos S. and Takala, Jarmo and Martinez, Jose Ignacio},
title = {Customized Exposed Datapath Soft-Core Design Flow with Compiler Support},
booktitle = {Proceedings of the 2010 International Conference on Field Programmable Logic and
Applications},
series = {FPL '10},
year = {2010},
isbn = {978-0-7695-4179-2},
pages = {217--222},
numpages = {6},
url = {http://dx.doi.org/10.1109/FPL.2010.51},
doi = {10.1109/FPL.2010.51},
acmid = {1933795},
publisher = {IEEE Computer Society},
address = {Washington, DC, USA},
}
Publications about TTA
Journal Papers
2010
- Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, and Jarmo Takala,
Programmable and Scalable Architecture for Graphics Processing Units,
Transactions on HiPEAC: Volume 5, Issue 3
2008
- Pertti Kellomäki, Vladimir Guzma, Jarmo Takala,
“Safe Pre-Pass Software Bypassing for Transport Triggered Processors” ,
Acta Technica Napocensis, vol. 49, no. 3, 2008 - special issue, pp.5-10 link to publishers page
Conference and Workshop Papers
2009
- L. Nurmi, P. Salmela, P. Kellomäki, P. Jääskeläinen, J. Takala
"Reconfigurable Video Decoder with Transform Acceleration". in Proc. of the 2009 IEEE Workshop on Signal Processing Systems, SIPS 2009, October 7-9, Tampere, Finland. Link to the publisher's page. - V. Guzma, T. Pitkänen, P. Kellomäki, J. Takala,
"Reducing Processor Energy Consumption by Compiler Optimization". in Proc. of the 2009 IEEE Workshop on Signal Processing Systems, SIPS 2009, October 7-9, Tampere, Finland. - Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala,
"Programmable and Scalable Architecture for Graphics Processing Units". Workshop of SAMOS IX:
Embedded Computer Systems: Architectures, Modeling, and Simulation (Samos, Greece, July 2009). (PDF available)
2008
- V. Guzma, P. Jääskeläinen, P. Kellomäki, and J. Takala,
“Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic,”
in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 8th Int. Workshop SAMOS VIII.,
M. Bereković, N. Dimopoulos, and S. Wong, Eds., Volume 5114, pp. 23–32. Springer-Verlag, Berlin, Germany, 2008 (PDF available) - Pekka Jääskeläinen, Heikki Kultala, Teemu Pitkänen, and Jarmo Takala,
“Reducing the Overheads of Hardware Acceleration Through Datapath Integration”
in Electronic Imaging 2008 (San Jose, USA, January 2008) (pdf available)
2007
- J.K. Tanskanen, T. Pitkänen, R. Mäkinen, and Jarmo Takala,
"Parallel Memory Architecture for TTA Processor" ,
in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS VII.,
S. Vassiliadis, M. Bereković, T.D. Hämäläinen, Volume LNCS 4599, pp. 233–240. Springer-Verlag, Berlin, Germany, 2007 (pdf) Link to the publisher's page. - T. Pitkänen, T. Partanen, and Jarmo Takala,
"Low-Power Twiddle Factor Unit for FFT Computation" ,
in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS VII.,
S. Vassiliadis, M. Bereković, T.D. Hämäläinen, Volume LNCS 4599, pp. 233–240. Springer-Verlag, Berlin, Germany, 2007 (pdf) Link to the publisher's page.
2006
- T. Pitkänen, R. Mäkinen, J. Heikkinen, T. Partanen, and J. Takala,
"Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform",
in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 6th Int. Workshop SAMOS VI,
S. Vassiliadis, S. Wong, T.D. Hämäläinen, Volume LNCS 4017, pp. 227–236. Springer-Verlag, Berlin, Germany, 2006 (pdf) - P. Salmela, P. Jääskeläinen, T. Järvinen, and J. Takala,
"Software pipelining support for transport triggered architecture processors",
in Embedded Computer Systems: Architectures, Modeling, and Simulation Proc. 6th Int. Workshop SAMOS VI, Lecture Notes in Computer Science - T. Pitkänen, R. Mäkinen, J. Heikkinen, T.Partanen, J. Takala,
"Transport triggered architecture processor for mixed-radix FFT",
in Proc. Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA (2006) (pdf) - P. Salmela, R. Mäkinen, P. Jääskeläinen, and J. Takala,
"Loop scheduling for transport triggered architecture processors",
in International Symposium on System-on-Chip (SoC), Tampere, Finland, Nov. 13-16, 2006, pp. 45-48.
2005
- J. Heikkinen, J. Takala, and H. Corporaal,
"Dictionary-Based Program Compression on TTAs: Effects on Area and Power Consumption",
in Proc. IEEE Workshop on Signal Processing Systems, Athens, Greece, Nov. 2-4, 2005, pp. 479-484. (pdf) - T. Pitkänen, T. Rantanen, A. Cilio, and J. Takala,
"Hardware Cost Estimation for Application-Specific Processor Design",
in Embedded Comput. Syst.: Architectures Modeling Simulation, Proc. 5th Int. Workshop SAMOS V,
T. D. Hämäläinen, A. D. Pimentel, J. Takala, and S. Vassiliadis, Eds. Lecture Notes in Computer Science,
vol. LNCS 3553, pp. 212-221. Springer-Verlag, Berlin, Germany, 2005. (pdf) - P. Salmela, T. Järvinen, T. Sipilä, and J. Takala,
"256-state rate 1/2 Viterbi decoder on TTA processor",
in proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Samos, Greece, 23-25 Jul. 2005, pp. 370-375. - P. Salmela, T. Järvinen, T. Sipilä, and J. Takala,
"Scalable FIR filtering on transport triggered architecture processor",
in proceedings of the International Symposium on Signals, Circuits and Systems (ISSCS 2005), Iasi, Romania, 14-15 Jul. 2005, pp. 493-496. - J. Heikkinen, A. Cilio, J. Takala, and H. Corporaal,
"Dictionary-Based Program Compression on Transport Triggered Architectures",
in Proc. IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 1122-1125. (pdf)
2004
- J. Heikkinen, P. Kuukkanen, and J. Takala,
"Bitwise and Dictionary Modeling for Code Compression on Transport Triggered Architectures",
in WSEAS Trans. on Circuits and Systems, vol. 3, iss. 9, pp. 1750-1755, Nov. 2004. (pdf)
2003
- R. Mäkelä, J. Takala, and O. Vainio,
"Analysis of Different bus Architectures for Transport Triggered Architectures",
in Proc. 21st Norchip Conf., Riga, Latvia, Nov. 10-11, 2003, pp. 56-59. (pdf) - J. Heikkinen, T. Rantanen, A. Cilio, J. Takala, and H. Corporaal,
"Immediate Optimization for Compressed Transport Triggered Architecture Instructions",
in Proc. Int. Symp. on System-on-Chip, Tampere, Finland, Nov. 19-21 2003, pp. 65-68. (pdf) - J. Heikkinen, T. Rantanen, A. Cilio, J. Takala, and H. Corporaal,
"Evaluating Template-Based Instruction Compression on Transport Triggered Architectures",
in Proc. Int. Workshop on System-on-Chip for Real-Time Applications, Calgary, Canada, June 30 - July 2 2003, pp. 192-195. (pdf)
2002
- J. Heikkinen, J. Sertamo, T. Rautiainen and J. Takala,
"Design of Transport Triggered Architecture Processor for Discrete Cosine Transform",
in Proc. 15th Ann. IEEE Int. ASIC/SOC Conf., Rochester, NY, U.S.A., Sept. 25-28 2002, pp. 87-91. (pdf) - J. Heikkinen, J. Takala and J. Sertamo,
"Code Compression on Transport Triggered Architectures",
in Proc. Int. Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 6-7 2002, pp. 186-195. (pdf) - J. Heikkinen, J. Takala, A. Cilio and H. Corporaal,
"On Efficiency of Transport Triggered Architectures",
in Advances in Systems Engineering, Signal Processing and Communications, N. Mastorakis, Ed.,
pp. 25-29. WSEAS Press, New York, NY, U.S.A., 2002. (pdf)
Master's Theses
- Risto Mäkinen:
Fast Fourier Transform on Transport Triggered Architectures (October, 2005) (pdf) - Teemu Pitkänen:
Experiments of TTA on ASIC Technology (August, 2005) (pdf) - Jari Heikkinen:
DSP Applications on Transport Triggered Architectures (May, 2001) (pdf)
Dissertations
- Perttu Salmela:
Implementations of Baseband Functions for Digital Receivers (August, 2009) (link) - Jari Heikkinen:
Program Compression in Long Instruction Word Application-Specific Instruction-Set Processors (December, 2007) (pdf)
Technical Reports
- Miika Niiranen: Transport Triggered Architectures on FPGA (October, 2004) (pdf)
Publications about the toolset
Journal Papers
2011
- Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, and Jarmo Takala,
OpenCL-based Design Methodology for Application-Specific Processors,
Transactions on HiPEAC: Volume 5, Issue 4
2007
- Pekka Jääskeläinen, Vladimír Guzma, Viljami Korhonen,
“Resource Conflict Detection in Simulation of Function Unit Pipelines” (extended version), in JSA Special Issue on SAMOS 2007, Elsevier. (pdf available)
Conference and Workshop Papers
2011
- Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala
"Operation Set Customization in Retargetable Compilers".
Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 6-9 Nov 2011, Pacific Grove, California (pdf available)
- Pekka O. Jääskeläinen, Erno O. Salminen, Carlos S. de La Lama, Jarmo H. Takala, and Jose Ignacio Martinez,
"TCEMC: A Co-Design Flow for Application-Specific Multicores".
in Proc. of IC-SAMOS 2011: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, July 18-21, Samos, Greece (download)
2010
- Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Jarmo Takala,
"Design methodology for accelerating software executions with FPGA",
in SiPS 2010 IEEE Workshop on Signal Processing Systems, San Francisco, USA, October 2010 Link to the publisher's page. - Otto Esko, Pekka Jääskeläinen, Pablo Huerta,
Carlos S. de La Lama, Jarmo Takala, Jose Ignacio Martinez,
“Customized Exposed Datapath Soft-Core Design Flow with Compiler Support”,
in 20th International Conference on Field Programmable Logic and Applications, Milano, Italy, August-September 2010, (PDF available) - Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala,
“OpenCL-based Design Methodology for Application-Specific Processors”,
in SAMOS X: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July 2010 (PDF available)
2008
- Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö,
"Reducing Context Switch Overhead with Compiler-Assisted Threading",
in The 3rd International Workshop on Embedded Software Optimization, Shanghai, China, Dec, 2008 (PDF available)
2007
- P. Jääskeläinen, V. Guzma, and J. Takala,
"Resource Conflict Detection in Simulation of Function Unit Pipelines" ,
in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS VII.,
S. Vassiliadis, M. Bereković, T.D. Hämäläinen, Volume LNCS 4599, pp. 233–240. Springer-Verlag, Berlin, Germany, 2007 (pdf) Link to the publisher's page. - P. Jääskeläinen, V. Guzma, A. Cilio and J. Takala,
"Codesign Toolset for Application-Specific Instruction-Set Processors",
in Multimedia on Mobile Devices, San Jose, California, USA, Jan 2007, Proc. SPIE Vol. 6507, 65070X. (pdf availale)
Dissertations
- Pekka Jääskeläinen:
From Parallel Programs to Customized Parallel Processors (September, 2012) (download)
Master's Theses
- Timo Viitanen:
Floating-Point Arithmetic in Transport Triggered Architectures (December, 2012) (link) - Otto Esko:
ASIP Integration and Verification Flow (June, 2011) (link) - Veli-Pekka Jääskeläinen:
Retargetable Compiler Backend for Transport Triggered Architectures (Feb, 2010) (pdf) - Jari Mäntyneva:
Automated Design Space Exploration of Transport Triggered Architectures (July, 2009) (pdf) - Viljami Korhonen:
Tools for Fast Design of Application-Specific Processors (January, 2009) (pdf) - Ari Metsähalme:
Instruction Scheduler Framework for Transport Triggered Architectures (April, 2008) (pdf) - Lasse Laasonen:
Program Image and Processor Generator for Transport Triggered Architectures (April, 2007) (pdf) - Mikael Lepistö:
Assembly Compiler for Parametrizable Parallel Processor (June, 2006) (pdf) - Pekka Jääskeläinen:
Instruction Set Simulator for Transport Triggered Architectures (September, 2005) (pdf)
Bachelor's Theses
- Otto Esko:
Siirtoliipaistujen prosessorien käyttäminen FPGA-pohjaisissa järjestelmäpiireissä (Utilizing Transport-Triggered Processors on FPGA-based System-on-Chip) (March, 2011) (pdf)
Related publications
Conference and Workshop Papers
2011
- Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala,
"Customizable Datapath Integrated Lock Unit,"
in Proc. of International Symposium on System on Chip 2011, Tampere, Finland, October 31-November 2, 2011 (pdf available) - Vladimír Guzma, Teemu Pitkänen, Jarmo Takala,
"Effects of Loop Unrolling and Use of Instruction Buffer on Processor Energy Consumption,"
in Proc. of International Symposium on System on Chip 2011, Tampere, Finland, October 31-November 2, 2011 - Vladimír Guzma, Teemu Pitkänen, and Jarmo H. Takala,
"Instruction Buffer with Limited Control Flow and Loop Nest Support,"
in Proc. of IC-SAMOS 2011: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, July 18-21, Samos, Greece.
2008
- Guzma, V.; Bhattacharyya, S.S.; Kellomaki, P.; Takala, J.,
"Trade-offs in mapping high-level dataflow graphs onto ASIPs,"
System-on-Chip, 2008. SOC 2008. International Symposium on , vol., no., pp.1-4, 5-6 Nov. 2008 URL: link to publishers page - Guzma, V.; Bhattacharyya, S.S.; Kellomaki, P.; Takala, J.,
"An integrated ASIP design flow for digital signal processing applications,"
Applied Sciences on Biomedical and Communication Technologies, 2008. ISABEL '08. First International Symposium on , vol., no., pp.1-5, 25-28 Oct. 2008 URL: link to publishers page
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