In order to add multiple TTA cores to your system level design, there are two useful switches in the Processor Generator and Program Image Generator tools.
One of them is -shared-files-dir which can be used to define a directory to which HDL files that can be shared between multiple TTAs are copied. This avoids name clashes, e.g. on FU names when two or more TTAs use the same implementation.
The second useful switch is -entity-name. This switch allows naming the generated core in the HDL files with a custom name. The name string is also inserted to all the core-specific component names to make them unique to avoid name clashes in HDL compilation of the system. It should be noted that the Program Image Generator (generatebits) also supports the -entity-name switch and the same entity name should be given for both tools to produce functioning TTA cores.
Using these switches, generating cores to designs with multiple TTAs can be done by using a shared HDL directory for all the cores (-shared-files-dir) and then naming each core with a different entity name (-entity-name) to avoid name clashes. How the cores are connected and the generation of the shared memory hierarchy is currently out of scope of TCE. While these switches assist in HDL generation of multi-TTA designs, the designer can also simulate multi-TTA designs at system level by using the TCE SystemC API (see Section 6.2).
Pekka Jääskeläinen 2016-11-24