This tutorial will cover TTA core generation and integration with a Zynq-7000 series SoC, but the workflow should adapt quite well for other AXI4-capable Xilinx SoCs.
The command to generate a processor core with an AlmaIF wrapper is as follows:
generateprocessor -d onchip -f onchip -e tta_core -i mach.idf -g AlmaIFIntegrator -o proge-out -p program.tpef mach.adf
generatebits -e tta_core -x proge-out mach.adf
To create a new project in Vivado, select File>New project from the menu bar. You will be presented with a window, where you can configure the project to be created. Click Next and set the project name and location to your preference. On the next screen, pick RTL Project and click Next. Select the proge-out folder and verify the Include files from subdirectories checkbox is checked. No action is needed for the next two screens, so you can click past them. Select the part you intend to use for the project from the list, click Next and Finish.
You should now have a fresh project with the TTA sources included.
Navigate to Flow>Create Block Design and name it toplevel. Right click on the design, select Add IP and add a ZYNQ7 Processing System block. Next, add the TTA cores. Again, right click on the design, but this time choose Add block.... Since our entity name was tta_core, the AlmaIF wrapper was named tta_core_toplevel. Add that, and repeat once.
You should now have two TTA cores and one ZYNQ7 Processing System in your block design. We will need to connect these together. Luckily, Vivado will recognize the AXI4 bus on our AlmaIF wrapper, and will offer to connect it for us. Right click on an empty part of the block design and select Run block automation, Click OK. Right click on the block design again and select Run connection automation. Check the All Automation checkbox and click OK.
After this, Vivado has picked address spaces for the cores. You can see these from the Address Editor tab. You will need these addresses to control the cores from the hard processor cores.
You will notice that the TTA cores' asynchronous reset has been left unconnected. We can actuate a synchronous reset through AlmaIF, so we can connect these to a constant high signal. Right click on the design, select Add IP and add the Constant IP block. Right click on the newly created block and select Customize IP. Set both Width and Value to 1. Connect the output to both cores' asynchronous reset pin.
You may customize the TTA cores' clock frequency by right clicking on the ZYNQ7 Processing System block and selecting Customize IP. The FPGA fabric clock frequencies can be set under Clock Configuration.
Our block design is ready, but we'll have to create a wrapper for it before it can be synthesized. Select Flow>Project Manager from the menu bar. You can see the toplevel block design in the sources window. Right click on it and select Create HDL Wrapper. The default setting works for us, click OK. Right click on the newly created toplevel_wrapper and select Set as Top.
You can now select Flow>Generate Bitstream from the menu bar. This will run the design through synthesis and implementation, and give you a bitstream file with which you can program the FPGA fabric on your SoC.
Pekka Jääskeläinen 2018-03-12