Processor Generator gives a warning message if the operation codes in FU are not numbered according to the alphabetical order of the operations. The VHDL implementation and the HDB entry of the FU should be fixed to use this kind of opcode numbering. See section 4.11.1 for more details.
RTL simulation, especially with GHDL, requires a large amount of memory when simulating processors with large address spaces. One workaround is to lower the memory address widths for the address spaces in the simulated processor.