TTA-based Co-Design Environment (TCE) is a toolset for designing and programming customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
News and updates
October 20th, 2016: New publications added
It's been too long time since a new publication page update. The following new publications are now found in proceedings and published journal issues:
- Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Janne Helkala, Jarmo Takala:
"Improving Code Density with Variable Length Encoding Aware Instruction Scheduling",
in Journal of Signal Processing Systems, September 2016, vol. 84, issue 3 (download).
- Tomi Äijö, Pekka Jääskeläinen, Tapio Elomaa, Jarmo Takala:
"Integer Linear Programming-Based Scheduling for Transport Triggered Architectures",
in ACM Transactions on Architecture and Code Optimization, January 2016, vol. 12, issue 4 (download).
- Heikki Kultala, Joonas Multanen, Pekka Jääskeläinen, Timo Viitanen, and Jarmo Takala:
"Impact of Operand Sharing to the Processor Energy Efficiency",
in CADS: 18Th CSI International Symposium on Computer Architecture & Digital Systems (Tehran, Iran, October 2015) (download).
- Ville Korhonen , Pekka Jääskeläinen, Matias Koskela, Jarmo Takala:
"Rapid Customization of Image Processors Using Halide",
in GlobalSIP: 3rd IEEE Global Conference on Signal & Information Processing (Orlando, Florida, December 2015) (download).
- Joonas Multanen, Timo Viitanen, Henry Linjamäki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila and Tommi Zetterman:
"Power Optimizations for a Transport Triggered SIMD Processor",
in SAMOS XV: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2015) (download).
March 3rd, 2016: TCE 1.13 released
A new version of the toolset is now available for download.
November 25th, 2015: moved to git and Github
TCE development was moved from Bazaar and Launchpad to Git and Github.
About TTA-based Co-Design Environment
As part of the project we are developing a codesign toolset using TTA as the architecture template. The toolset is called TTA-based Co-Design Environment (TCE).
TCE is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
TCE has been developed in the Tampere University of Technology since the early 2003.
Further reading: LLVM project blog post about TCE.
- LLVM based, Clang as the default frontend
- OpenCL support via the pocl project
- Basic block instruction scheduler (top-down and bottom-up)
- Delay slot filling
- Software bypassing
- (experimental) Operand sharing
- Custom operation support
- Parallel TTA assembler
- Software and hardware floating point support
- Basic debugging info support
- Multiple address space support
- Support for native computation on half precision floats (fp16)
- Graphical and command line user interfaces
- Interpretive debugging engine for cycle stepping
- Static compiled engine for fast simulation with basic block granularity (but cycle count accuracy)
- Dynamic compiled engine for improved startup time with fast simulation
- SystemC integration API
- Processor and Program Image Generation:
- Support for generating implementation for the designed processor as VHDL. Experimental support for Verilog.
- Generates bit image of the program (supported formats include the Altera MIF)
- Dictionary-based instruction compression
- Automated generation of the files needed to integrate the core to different FPGA platforms.
- IP-XACT 1.5 support
- Design space exploration:
- Automated, manual and semi-automatic algorithm implementations
- Tools that allow easy modification of the target architecture
- Automated search of the connectivity design space
- Integrated Development Environment tools:
- Graphical user interface (GUI) for editing architecture resources
- GUI for editing operation set definitions