ProcessorWrapperBlock.hh

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/*
 Copyright (c) 2002-2015 Tampere University.
 
 This file is part of TTA-Based Codesign Environment (TCE).
 
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 all copies or substantial portions of the Software.
 
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/*
 * @file ProcessorWrapperBlock.hh
 *
 * Implementation/Declaration of ProcessorWrapperBlock class.
 *
 * Created on: 7.9.2015
 * @author Henry Linjam�ki 2015 (henry.linjamaki-no.spam-tut.fi)
 * @note rating: red
 */
 
#ifndef PROCESSORWRAPPERBLOCK_HH
#define PROCESSORWRAPPERBLOCK_HH
 
#include "BaseNetlistBlock.hh"
 
#include "Exception.hh"
 
namespace ProGe {
 
class NetlistPortGroup;
class ProGeContext;
class MemoryBusInterface;
 
/*
 * Netlist Block for test bench that wraps TTA-(multi)core block and necessary
 * data and instruction memories.
 */
class ProcessorWrapperBlock: public BaseNetlistBlock {
public:
    ProcessorWrapperBlock() = delete;
    ProcessorWrapperBlock(
        const ProGeContext& context,
        const BaseNetlistBlock& processorBlock);
    virtual ~ProcessorWrapperBlock();
 
    virtual void write(
        const Path& targetBaseDir, HDL targetLang = VHDL) const override;
 
private:
 
    void addInstructionMemory(const NetlistPortGroup&);
    void addDataMemory(const MemoryBusInterface&);
    void addDataMemory2(const MemoryBusInterface&);
    void connectLockStatus(
        const NetlistPort& topPCInitPort);
    void connectPCInit(
        const NetlistPort& topPCInitPort);
 
    void handleUnconnectedPorts();
 
    const ProGeContext& context_;
    /// The target TTA processor
    BaseNetlistBlock* coreBlock_;
    unsigned imemCount_ = 0;
};
 
} /* namespace ProGe */
 
#endif /* PROCESSORWRAPPERBLOCK_HH */