Classes
class	AndReduce

class	Assign

class	Asynchronous

class	Behaviour

class	BinaryConstant

class	BinaryLiteral

class	BinaryOp

class	BitwiseAnd

class	BitwiseNot

class	BitwiseOr

class	BitwiseXor

class	Case

class	CodeBlock

class	DefaultAssign

class	DefaultCase

class	Equals

class	Ext

class	Generatable

class	HDLOperation

class	If

class	InPort

class	IntegerConstant

class	LHSSignal

class	LHSValue

class	LogicalAnd

class	LogicalNot

class	LogicalOr

class	LogicVariable

class	Module

class	NewLine

class	NotEquals

class	Option

class	OrReduce

class	OutPort

class	Parameter

class	Port

class	RawCodeLine

class	Reduce

class	Register

class	SequentialStatement

class	Sext

class	SignedVariable

class	Splice

class	Switch

class	Synchronous

class	UnaryOp

class	UnsignedVariable

class	Variable

struct	Width

class	Wire

class	XorReduce

Enumerations
enum	Language { Language::VHDL, Language::Verilog }

enum	WireType { WireType::Auto, WireType::Vector }

enum	Direction { Direction::In, Direction::Out }

enum	ResetOption { ResetOption::Mandatory, ResetOption::Optional }