9 Hardware Database Tester

HDB tester is an utility program which tests that a function unit or register file implementation in HDB is equal to its simulation model. Tester can be used to test one or all implementations from HDB.

HDB tester uses simulation behaviour models to create reference output values from input stimulus. Then it creates an RTL testbench with the unit under test and compares the output to the reference. HDB tester requires an RTL simulator to be installed. Currently 'ghdl' and 'modelsim' are supported.

1 Usage

HDB tester executable is called testhdb and it is used as follows:

testhdb <options> hdb-file

HDB tester accepts following command line options:

	Short Name		Long Name		Description
	f		fuid		Entry id of FU component to be tested. If this is or RF ID are not defined whole HDB will be tested.
	d		leave-dirty		Don't delete created files
	r		rfid		Entry id of RF component to be tested. If this is or FU ID are not defined whole HDB will be tested.
	s		simulator		HDL simulator used to simulate testbench. Accepted values are 'ghdl' and 'modelsim'. Default is ghdl. Simulator executable must be found from PATH.
	v		verbose		Enable verbose output. Prints all executed commands.

Example: test all FU and RF implementations in HDB:

testhdb asic_130nm_1.5V.hdb

Example: test FU implementation id 1 from HDB, keep testbench files and print commands:

testhdb -d -v -f 1 asic_130nm_1.5V.hdb

Example: test RF implementation id 125 from HDB and use modelsim as RTL simulator:

testhdb -r 125 -s modelsim asic_130nm_1.5V.hdb

If 'verbose' option is not defined HDB tester won't output anything when test passes.

2 Test conditions

Function units is not tested if it meets one of these conditions:

1. Function unit does not have an architecture in HDB

2. Function unit does not have an implementation in HDB

3. Function unit accesses memory

4. Function unit is not pipelined

5. Function unit has external ports

6. Function unit has only one port

Register file is not tested if it meets one of these conditions:

1. register file does not have an architecture in HDB

2. Register file does not have an implementation in HDB

3. Register file does not have a read port

4. Register file does not have a write port

5. Register file has bidirectional port(s)

6. Register file does not have latency of 1 cycle