TestBenchBlock.cc

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/*
 Copyright (c) 2002-2015 Tampere University.
 
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/*
 * @file TestBenchBlock.cc
 *
 * Implementation of TestBenchBlock class.
 *
 * Created on: 7.9.2015
 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
 * @note rating: red
 */
 
#include "TestBenchBlock.hh"
 
#include "ProcessorWrapperBlock.hh"
 
#include "Machine.hh"
#include "MachineInfo.hh"
 
#include "HDLTemplateInstantiator.hh"
#include "FileSystem.hh"
#include "Environment.hh"
#include "Conversion.hh"
 
namespace ProGe {
 
/**
 * Construct The test bench for the core TTA processor.
 *
 * The test bench creation is limited to TTAs with one address space for
 * instruction and address spaces for data shared by one LSU at most.
 *
 * @param context The context for deriving necessary information about the
 *                core.
 * @param coreBlock The DUT for test bench
 * @exception Thrown if the test bench can not be created.
 */
TestBenchBlock::TestBenchBlock(
    const ProGeContext& context, const BaseNetlistBlock& coreBlock)
    : BaseNetlistBlock("testbench", ""), context_(context), proc_(nullptr) {
    using namespace TTAMachine;
 
    std::map<std::string, unsigned> ASUserCounts;
    std::map<std::string, unsigned> lockFUCounts;
 
    for (auto fu : MachineInfo::findLockUnits(context.adf())) {
        if (fu->hasAddressSpace()) {
            lockFUCounts[fu->addressSpace()->name()]++;
        }
    }
 
    for (auto fu : context.adf().functionUnitNavigator()) {
        if (fu->hasAddressSpace()) {
            ASUserCounts[fu->addressSpace()->name()]++;
        }
    }
 
    for (auto asUserCount : ASUserCounts) {
        unsigned LSUCount(asUserCount.second);
 
        if (lockFUCounts.count(asUserCount.first) > 0) {
            LSUCount -= lockFUCounts[asUserCount.first];
        }
 
        if (LSUCount > 1) {
            THROW_EXCEPTION(NotAvailable,
                "Can not create test bench for TTA address spaces shared by "
                "multiple LSUs.");
        }
    }
    try {
        proc_ = new ProcessorWrapperBlock(context, coreBlock);
    } catch (Exception& e) {
        THROW_EXCEPTION(NotAvailable, e.errorMessage());
    }
}
 
TestBenchBlock::~TestBenchBlock() {
}
 
void
TestBenchBlock::write(const Path& targetBaseDir, HDL targetLang) const {
    // Check language compatibility //
    if (targetLang != VHDL) {
        THROW_EXCEPTION(NotAvailable, "Only VHDL is supported.");
    }
 
    HDLTemplateInstantiator instantiator(context_.coreEntityName());
 
    instantiator.replacePlaceholder("dut-entity", proc_->moduleName());
 
    if (context_.idf().icDecoderParameterValue("debugger") == "external") {
        instantiator.replacePlaceholder("proc-entity-db-signals",
                "db_pc_start : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);\n"
                "db_tta_nreset : in std_logic;\n"
                "db_lockrq     : in std_logic;");
 
        instantiator.replacePlaceholder("proc-instance-db-signals",
                "db_pc_start   => (others => '0'),\n"
                "db_tta_nreset => '1',\n"
                "db_lockrq     => '0',");
    }
 
    FileSystem::createDirectory(targetBaseDir/"tb");
 
    Path progeDataDir(Environment::dataDirPath("ProGe"));
    instantiator.instantiateTemplateFile(
        progeDataDir/"tb"/"testbench.vhdl.tmpl",
        targetBaseDir/"tb"/"testbench.vhdl");
    instantiator.instantiateTemplateFile(
        progeDataDir/"tb"/"clkgen.vhdl",
        targetBaseDir/"tb"/"clkgen.vhdl");
 
    proc_->write(targetBaseDir, targetLang);
}
 
} /* namespace ProGe */