FUGen Class Reference

#include <FUGen.hh>

Collaboration diagram for FUGen:

Classes
struct	BaseOperation
struct	DAGConstant
struct	OperandConnection
struct	OperationSchedule
struct	OutputConnection

Public Member Functions
	FUGen ()=delete
	FUGen (const FUGen &)=delete
FUGen &	operator= (const FUGen &)=delete
	FUGen (const ProGeOptions &options, std::vector< std::string > globalOptions, IDF::FUGenerated &fug, const TTAMachine::Machine &machine, ProGe::NetlistBlock *core)

Static Public Member Functions
static void	implement (const ProGeOptions &options, std::vector< std::string > globalOptions, const std::vector< IDF::FUGenerated > &generatetFUs, const TTAMachine::Machine &machine, ProGe::NetlistBlock *core)

Private Types
typedef std::pair< std::string, std::string >	Replace

Private Member Functions
void	createOutputPipeline ()
void	addRegisterIfMissing (std::string name, int width, HDLGenerator::WireType wt=HDLGenerator::WireType::Auto)
std::string	findAbsolutePath (std::string file)
void	createFUHeaderComment ()
void	createMandatoryPorts ()
void	checkForValidity ()
void	createExternalInterfaces (bool genIntegrator)
void	createOperationResources ()
void	buildOperations ()
void	finalizeHDL ()
void	createImplementationFiles ()
void	copyImplementation (std::string file, std::string format, bool isSynthesizable)
void	parseOperations ()
void	scheduleOperations ()
void	createPortPipeline ()
void	createShadowRegisters ()
OperandConnection	subOpConnection (OperationDAG *dag, OperationDAGEdge *edge, bool isOutput)
int	DAGNodeOperandWidth (OperationDAGNode &node, int id, OperationDAG *dag)
void	readImplementation (std::string filename, std::string opName, std::deque< std::string > &sink)
void	prepareSnippet (std::string name, std::deque< std::string > statements, HDLGenerator::CodeBlock &sink, std::set< std::string > &addedStatements)
std::deque< std::string >	readFile (std::string filename)
std::vector< Replace >	buildReplaces (std::string opName)
std::string	replaceToken (std::string line, Replace replace)
bool	hasToken (std::string line, std::string token)
HDLGenerator::Language	selectedLanguage ()
std::string	opcodeSignal (int stage)
std::string	triggerSignal (int stage)
std::string	opcodeConstant (std::string operation)
std::string	operandSignal (std::string operation, int id)
std::string	operandPlaceholder (int id)
std::string	pipelineName (std::string port, int cycle)
std::string	pipelineValid (std::string port, int cycle)
std::string	subOpName (OperationNode *node)
std::string	constantName (ConstantNode *node, OperationDAG *dag)
std::string	constantName (DAGConstant dag)
bool	isLSUDataPort (const std::string &portName)
ProGe::Signal	inferLSUSignal (const std::string &portName) const

Private Attributes
int	maxLatency_
int	minLatency_
const ProGeOptions &	options_
std::vector< std::string >	globalOptions_
IDF::FUGenerated &	fug_
ProGe::NetlistBlock *	core_
HDLGenerator::Module	fu_
TTAMachine::FunctionUnit *	adfFU_
std::vector< std::string >	operations_
int	opcodeWidth_
std::string	moduleName_
ProGe::NetlistBlock *	netlistBlock_
std::unordered_map< std::string, BaseOperation >	baseOperations_
std::unordered_map< std::string, OperationSchedule >	scheduledOperations_
std::unordered_map< std::string, std::vector< Replace > >	replacesPerOp_
std::unordered_map< std::string, int >	operationCycles_
std::unordered_map< std::string, int >	implLatency_
std::unordered_map< std::string, OperationDAG * >	implementapleDAGs_
std::unordered_map< std::string, int >	subOpCount_
std::unordered_map< std::string, int >	dagConstantCount_
std::unordered_map< std::string, int >	resourceCount_
std::unordered_map< std::string, int >	pipelineLength_
std::unordered_map< std::string, ProGe::Direction >	portDirection_
std::unordered_multimap< std::string, OutputConnection >	portInputs_
std::unordered_map< int, int >	nodeImplementations_
std::unordered_map< int, DAGConstant >	dagConstants_
std::vector< std::string >	resourceInputs_
std::vector< std::string >	resourceOutputs_
std::unordered_set< std::string >	extIfaces_
std::set< std::pair< std::string, std::string > >	extOutputs_
std::unordered_set< std::string >	extInputs_
std::vector< HDB::Variable >	renamedVariables_
std::vector< HDB::Variable >	renamedGlobalSignals_
std::string	triggerPort_
std::vector< std::string >	registers_
bool	useGlockRequest_ = false
bool	useGlock_ = false
HDLGenerator::Behaviour	behaviour_
bool	frontRegistered_ = false
bool	middleRegistered_ = false
bool	backRegistered_ = false
int	addressWidth_ = 0
bool	isLSU_ = false

Detailed Description

Definition at line 58 of file FUGen.hh.

Member Typedef Documentation

Replace

typedef std::pair<std::string, std::string> FUGen::Replace

private

Definition at line 98 of file FUGen.hh.

Constructor & Destructor Documentation

FUGen() [1/3]

FUGen::FUGen ( )

delete

FUGen() [2/3]

FUGen::FUGen ( const FUGen &  )

delete

FUGen() [3/3]

FUGen::FUGen ( const ProGeOptions &  options, std::vector< std::string >  globalOptions, IDF::FUGenerated &  fug, const TTAMachine::Machine &  machine, ProGe::NetlistBlock *  core  )

inline

Definition at line 63 of file FUGen.hh.

                                                                  :
            options_(options),
            globalOptions_(globalOptions),
            fug_(fug),
            core_(core),
            fu_(StringTools::stringToLower("fu_" + fug.name())),
            adfFU_(machine.functionUnitNavigator().item(fug.name())),
            operations_(),
            opcodeWidth_(MathTools::requiredBits(adfFU_->operationCount()-1)),
            moduleName_("fu_" + fug_.name()) {
 
        // Find the netlistblock
        for (size_t i = 0; i < core_->subBlockCount(); ++i) {
            std::string name = core_->subBlock(i).moduleName();
            if (name == StringTools::stringToLower(moduleName_)) {
                netlistBlock_ = &core_->subBlock(i);
                break;
            }
        }
 
        if (adfFU_->hasAddressSpace()) {
            auto as = adfFU_->addressSpace();
            addressWidth_ = MathTools::requiredBits(as->end());
        }
    }

References TTAMachine::FunctionUnit::addressSpace(), addressWidth_, adfFU_, core_, TTAMachine::FunctionUnit::hasAddressSpace(), ProGe::BaseNetlistBlock::moduleName(), moduleName_, netlistBlock_, MathTools::requiredBits(), StringTools::stringToLower(), ProGe::NetlistBlock::subBlock(), and ProGe::NetlistBlock::subBlockCount().

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Member Function Documentation

addRegisterIfMissing()

void FUGen::addRegisterIfMissing ( std::string  name, int  width, HDLGenerator::WireType  wt = HDLGenerator::WireType::Auto  )

private

Definition at line 1377 of file FUGen.cc.

                                                                  {
    if (!ContainerTools::containsValue(registers_, name)) {
        fu_ << Register(name, width, wt, ResetOption::Optional);
        registers_.emplace_back(name);
    }
}

References ContainerTools::containsValue(), and HDLGenerator::Optional.

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buildOperations()

void FUGen::buildOperations ( )

private

Definition at line 672 of file FUGen.cc.

                       {
    Asynchronous operationCp("operations_actual_cp");
    CodeBlock defaultValues;
    CodeBlock defaultSnippets;
    CodeBlock triggeredSnippets;
 
    for (auto&& d : extOutputs_) {
        operationCp << DefaultAssign(d.first, d.second);
    }
 
    for (std::string signal : resourceInputs_) {
        // Zero initialize this configuration to avoid simulation warnings
        if (isLSU_ && minLatency_ < 3) {
            operationCp << DefaultAssign(signal, "0");
        } else {
            operationCp << DefaultAssign(signal, "-");
        }
    }
 
    for (auto&& pair : dagConstants_) {
        auto spec = pair.second;
        std::string name = constantName(spec);
        int width = MathTools::requiredBitsSigned(spec.value);
        fu_ << BinaryConstant(name, width, spec.value);
    }
 
    for (std::string signal : resourceOutputs_) {
        operationCp.reads(signal);
    }
 
    for (std::string signal : extInputs_) {
        operationCp.reads(signal);
    }
 
    std::set<std::string> defaultStatements;
    for (auto&& pair : scheduledOperations_) {
        auto schedule = pair.second;
        std::string name = pair.first;
 
        for (int id : schedule.results) {
            std::string source = operandSignal(name, id);
            // Zero initialize this configuration to avoid simulation warnings
            if (isLSU_ && minLatency_ < 3) {
                defaultValues.append(DefaultAssign(source, "0"));
            } else {
                defaultValues.append(DefaultAssign(source, "-"));
            }
        }
 
        for (auto&& operand : schedule.operands) {
            int id = operand.id;
 
            std::string source = operand.signalName;
            std::string destination = operandSignal(name, id);
            if (operand.portWidth > operand.operandWidth) {
                defaultValues.append(Assign(
                    destination,
                    Splice(source, operand.operandWidth - 1, 0)));
            } else if (operand.portWidth < operand.operandWidth) {
                defaultValues.append(Assign(
                    destination,
                    Ext(source, operand.operandWidth, operand.portWidth)));
            } else {
                defaultValues.append(Assign(destination, LHSSignal(source)));
            }
 
            if (!operand.isOutput) {
                operationCp.reads(destination);
            }
        }
 
        replacesPerOp_[name] = buildReplaces(name);
 
        std::string baseOp = schedule.baseOp;
        auto& initial = baseOperations_[baseOp].initial;
        if (!initial.empty()) {
            prepareSnippet(name, initial, defaultSnippets, defaultStatements);
        }
    }
 
    for (int cycle = 0; cycle <= maxLatency_; ++cycle) {
        Switch opSwitch(LHSSignal(opcodeSignal(cycle)));
        bool emptySwitch = true;
 
        for (std::string op : operations_) {
            CodeBlock onTrigger;
            bool emptyBlock = true;
            auto schedule = scheduledOperations_[op];
 
            std::vector<std::string> schedules = schedule.subOperations;
            schedules.push_back(op);
 
            for (std::string subop : schedules) {
                auto schedule = scheduledOperations_[subop];
                std::string baseOp = schedule.baseOp;
                if (schedule.initialCycle == cycle) {
                    auto& impl = baseOperations_[baseOp].implementation;
                    if (!impl.empty()) {
                        std::set<std::string> statements;
                        prepareSnippet(subop, impl, onTrigger, statements);
                    }
                    emptyBlock = false;
                }
 
                if (schedule.finalCycle == cycle) {
                    auto& postOp = baseOperations_[baseOp].postOp;
                    if (!postOp.empty()) {
                        std::set<std::string> statements;
                        prepareSnippet(subop, postOp, onTrigger, statements);
                    }
                    emptyBlock = false;
                }
            }
 
            if (emptyBlock) {
                continue;
            }
 
            if (operations_.size() > 1) {
                Case opCase(opcodeConstant(op));
                opCase << onTrigger;
                opSwitch.addCase(opCase);
                emptySwitch = false;
            } else {
                If opIf(
                    Equals(
                        LHSSignal(triggerSignal(cycle)), BinaryLiteral("1")),
                    onTrigger);
                triggeredSnippets.append(opIf);
            }
        }
 
        if (!emptySwitch) {
            opSwitch.addCase(DefaultCase());
            If opIf(
                Equals(LHSSignal(triggerSignal(cycle)), BinaryLiteral("1")),
                opSwitch);
            triggeredSnippets.append(opIf);
        }
    }
 
    if (useGlock_) {
        operationCp.reads("glock_in");
    }
 
    if (useGlockRequest_) {
        defaultValues.append(Assign("glockreq", BinaryLiteral("0")));
    }
 
    for (auto&& v : renamedVariables_) {
        int w = std::stoi(v.width);
        if (v.type == "Logic") {
            operationCp.addVariable(LogicVariable(v.name, w));
        } else if (v.type == "Unsigned") {
            operationCp.addVariable(UnsignedVariable(v.name, w));
        } else {
            operationCp.addVariable(SignedVariable(v.name, w));
        }
        // Zero initialize this configuration to avoid simulation warnings
        if (isLSU_ && minLatency_ < 3) {
            operationCp << DefaultAssign(v.name, "0");
        } else {
            operationCp << DefaultAssign(v.name, "-");
        }
    }
    for (auto&& s : renamedGlobalSignals_) {
        int w = std::stoi(s.width);
        fu_ << Wire(s.name, w);     // creates the signal declaration
        operationCp.reads(s.name);  // adds it to sensitivity list
        // Zero initialize this configuration to avoid simulation warnings
        if (isLSU_ && minLatency_ < 3) {
            operationCp << DefaultAssign(s.name, "0");
        } else {
            operationCp << DefaultAssign(s.name, "-");
        }
    }
 
    operationCp << defaultValues << defaultSnippets << triggeredSnippets;
    behaviour_ << operationCp;
}

References HDLGenerator::Switch::addCase(), HDLGenerator::Asynchronous::addVariable(), HDLGenerator::CodeBlock::append(), HDLGenerator::Asynchronous::reads(), and MathTools::requiredBitsSigned().

Referenced by implement().

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buildReplaces()

std::vector< FUGen::Replace > FUGen::buildReplaces ( std::string  opName )

private

Definition at line 395 of file FUGen.cc.

                                   {
    OperationSchedule& schedule = scheduledOperations_[name];
    std::string op = schedule.baseOp;
    std::vector<FUGen::Replace> replaces;
 
    replaces.emplace_back("glock", "glock_in");
    replaces.emplace_back("trigger", triggerSignal(schedule.initialCycle));
 
    for (auto&& operand : schedule.operands) {
        int id = operand.id;
        replaces.emplace_back(
            operandPlaceholder(id), operandSignal(name, id));
    }
    for (int id : schedule.results) {
        replaces.emplace_back(
            operandPlaceholder(id), operandSignal(name, id));
    }
 
    if (!baseOperations_.count(op)) {
        return replaces;
    }
 
    // Resources
    for (auto&& r : baseOperations_[op].resources) {
        std::string rName = StringTools::stringToLower(r.name);
        if (!schedule.resourceOffsets.count(rName)) {
            assert(false && "Couldn't find resource offset.");
        }
        int offset = schedule.resourceOffsets[rName];
 
        for (int i = 0; i < r.count; ++i) {
            int portID = i + 1;
            int resID = i + offset + 1;
            std::string file = findAbsolutePath(r.ipxact);
            ipxact::ModuleInfo resource = ipxact::parseComponent(file);
            for (auto&& p : resource.ports) {
                std::string pName = StringTools::stringToLower(p.name);
                std::string replace = pName + "_" + std::to_string(portID);
                std::string with =
                    rName + "_" + std::to_string(resID) + "_" + pName;
 
                replaces.emplace_back(replace, with);
            }
        }
    }
 
    // Variables
    for (auto&& v : baseOperations_[op].variables) {
        std::string replica;
        if (v.rename) {
            replica = name + "_" + v.name;
            replaces.emplace_back(v.name, replica);
        } else {
            bool nameFound = false;
            for (auto&& old_var : renamedVariables_) {
                if (old_var.name == v.name) {
                    nameFound = true;
                }
            }
            if (nameFound) {
                continue;
            }
            replica = v.name;
        }
        HDB::Variable var = {replica, v.width, v.type, v.rename};
        renamedVariables_.emplace_back(var);
    }
    // Global signals
    for (auto&& s : baseOperations_[op].globalsignals) {
        std::string replica;
        // Not renaming the signals allows them to be directly shared between
        // ops
        if (s.rename) {
            replica = name + "_" + s.name;
            replaces.emplace_back(s.name, replica);
        } else {
            // don't add the same signal multiple times
            bool nameFound = false;
            for (auto&& old_var : renamedGlobalSignals_) {
                if (old_var.name == s.name) {
                    nameFound = true;
                }
            }
            if (nameFound) {
                continue;
            }
            replica = s.name;
        }
 
        HDB::Variable var = {replica, s.width, s.type, s.rename};
        renamedGlobalSignals_.emplace_back(var);
    }
 
    return replaces;
}

References assert, FUGen::OperationSchedule::baseOp, FUGen::OperationSchedule::initialCycle, FUGen::OperationSchedule::operands, ipxact::parseComponent(), ipxact::ModuleInfo::ports, FUGen::OperationSchedule::resourceOffsets, FUGen::OperationSchedule::results, StringTools::stringToLower(), and HDB::Variable::width.

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checkForValidity()

void FUGen::checkForValidity ( )

private

Definition at line 365 of file FUGen.cc.

                        {
    // Check that we can implement the FU.
    // Cannot implement if FU has multioutput operation that has
    //  different latencies for the outputs.
    for (auto&& op : operations_) {
        TTAMachine::HWOperation* hwOp = adfFU_->operation(op);
        int hwOpOperands = hwOp->operandCount();
        int prevLatency = -1;
        for (int operand = 0; operand < hwOpOperands; ++operand) {
            TTAMachine::FUPort* fuPort = hwOp->port(operand + 1);
 
            if (!fuPort->isOutput()) {
                continue;
            }
 
            int latency = hwOp->latency(operand + 1);
            if (prevLatency == -1) {
                prevLatency = latency;
            } else if (prevLatency != latency) {
                // TODO: probably not true anymore, but needs to be tested
                throw std::runtime_error(
                    "FUGen cannot implement multioutput operations (" + op +
                    ") which have different latencies for"
                    " its outputs.");
            }
        }
    }
}

References TTAMachine::Port::isOutput(), TTAMachine::HWOperation::latency(), TTAMachine::HWOperation::operandCount(), and TTAMachine::HWOperation::port().

Referenced by implement().

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constantName() [1/2]

std::string FUGen::constantName ( ConstantNode *  node, OperationDAG *  dag  )

private

Definition at line 178 of file FUGen.cc.

                                                         {
    int id;
    std::string op = dag->operation().name();
    op = StringTools::stringToLower(op);
    if (dagConstants_.count(node->nodeID())) {
        id = dagConstants_[node->nodeID()].id;
    } else {
        if (!dagConstantCount_.count(op)) {
            dagConstantCount_[op] = 0;
        }
        id = dagConstantCount_[op];
        dagConstantCount_[op] += 1;
        dagConstants_[node->nodeID()] = {op, node->value(), id};
    }
    return constantName(dagConstants_[node->nodeID()]);
}

References OperationPimpl::name(), GraphNode::nodeID(), OperationDAG::operation(), StringTools::stringToLower(), and ConstantNode::value().

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constantName() [2/2]

std::string FUGen::constantName ( DAGConstant  dag )

private

Definition at line 196 of file FUGen.cc.

                                    {
    return "dag_" + dagc.operation + "_" + std::to_string(dagc.id) + "_c";
}

References FUGen::DAGConstant::id, and FUGen::DAGConstant::operation.

copyImplementation()

void FUGen::copyImplementation ( std::string  file, std::string  format, bool  isSynthesizable  )

private

Definition at line 267 of file FUGen.cc.

                                                            {
    file = findAbsolutePath(file);
    const std::string DS = FileSystem::DIRECTORY_SEPARATOR;
    std::string dir = options_.outputDirectory + DS;
    if (isSynthesizable) {
        dir += format == "VHDL" ? "vhdl" : "verilog";
    } else {
        dir += "blackbox" + DS;
        dir += format == "VHDL simulation" ? "vhdl" : "verilog";
    }
    std::string target =
        dir + FileSystem::DIRECTORY_SEPARATOR + FileSystem::fileOfPath(file);
    if (!FileSystem::fileExists(target)) {
        FileSystem::createDirectory(dir);
        FileSystem::copy(file, target);
    }
}

References FileSystem::copy(), FileSystem::createDirectory(), FileSystem::DIRECTORY_SEPARATOR, DS, FileSystem::fileExists(), and FileSystem::fileOfPath().

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createExternalInterfaces()

void FUGen::createExternalInterfaces ( bool  genIntegrator )

private

Definition at line 568 of file FUGen.cc.

                                                  {
    std::set<std::pair<ProGe::NetlistPort*, ProGe::NetlistPort*>> lsuPorts;
    Replace replaceAddress = {"addrw_c", std::to_string(addressWidth_)};
    for (auto&& ei : extIfaces_) {
        ipxact::BusInfo info = ipxact::parseBus(ei);
        for (auto&& port : info.ports) {
            std::string width = port.width;
            if (addressWidth_ > 0) {
                width = replaceToken(width, replaceAddress);
            }
            ProGe::Direction dir;
            if (port.direction == "out") {
                fu_ << OutPort(
                    port.name, width, HDLGenerator::WireType::Vector);
                extOutputs_.emplace(port.name, port.defaultValue);
                dir = ProGe::Direction::OUT;
            } else {
                fu_ << InPort(
                    port.name, width, HDLGenerator::WireType::Vector);
                extInputs_.emplace(port.name);
                dir = ProGe::Direction::IN;
            }
 
            std::string extName = moduleName_ + "_" + port.name;
            ProGe::NetlistPort* ext = NULL;
            ProGe::NetlistPort* internal = new ProGe::NetlistPort(
                port.name, width, ProGe::DataType::BIT_VECTOR, dir,
                *netlistBlock_);
            if (isLSUDataPort(extName) && !genIntegrator) {
                ext = new ProGe::NetlistPort(
                    extName, width, ProGe::DataType::BIT_VECTOR, dir, *core_,
                    inferLSUSignal(extName));
                lsuPorts.insert(std::make_pair(internal, ext));
            } else {
                ext = new ProGe::NetlistPort(
                    extName, width, ProGe::DataType::BIT_VECTOR, dir, *core_);
                core_->netlist().connect(*ext, *internal);
            }
        }
    }
    if (lsuPorts.empty()) {
        return;
    }
    // Handle LSU data ports.
    TCEString asName("");
    if (adfFU_->hasAddressSpace()) {
        asName = adfFU_->addressSpace()->name();
    }
 
    ProGe::NetlistPortGroup* dmemPortGroup = nullptr;
    for (auto portPair : lsuPorts) {
        dmemPortGroup =
            dmemPortGroup
                ? dmemPortGroup
                : (new ProGe::MemoryBusInterface(
                      ProGe::SignalGroupType::BYTEMASKED_SRAM_PORT, asName));
        dmemPortGroup->addPort(*portPair.second);
        core_->netlist().connect(*portPair.first, *portPair.second);
    }
    if (dmemPortGroup != nullptr) {
        core_->addPortGroup(dmemPortGroup);
        dmemPortGroup = nullptr;
    }
}

References ProGe::NetlistPortGroup::addPort(), ProGe::BIT_VECTOR, ProGe::BYTEMASKED_SRAM_PORT, HDB::IN, HDB::OUT, ipxact::parseBus(), ipxact::BusInfo::ports, and HDLGenerator::Vector.

Referenced by implement().

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createFUHeaderComment()

void FUGen::createFUHeaderComment ( )

private

Creates the header comment for fu.

Definition at line 228 of file FUGen.cc.

                             {
    fu_.appendToHeader("Function Unit: " + fug_.name());
    fu_.appendToHeader("");
    fu_.appendToHeader("Operations:");
 
    if (adfFU_->operationCount() > 1) {
        size_t maxOpNameLen = 0;
        for (int i = 0; i < adfFU_->operationCount(); ++i) {
            TTAMachine::HWOperation* hwop = adfFU_->operation(i);
            maxOpNameLen = std::max(maxOpNameLen, hwop->name().size());
        }
        int opDigits =
            static_cast<int>(std::ceil(std::log10(adfFU_->operationCount())));
        for (int i = 0; i < adfFU_->operationCount(); ++i) {
            TTAMachine::HWOperation* hwop = adfFU_->operation(i);
            operations_.emplace_back(hwop->name());
        }
        std::sort(operations_.begin(), operations_.end());
        int opcode = 0;
        for (auto&& op : operations_) {
            fu_ << BinaryConstant(opcodeConstant(op), opcodeWidth_, opcode);
            std::ostringstream comment;
            comment << boost::format(
                           " %-" + std::to_string(maxOpNameLen) + "s : %" +
                           std::to_string(opDigits) + "s") %
                           op % std::to_string(opcode);
            fu_.appendToHeader(comment.str());
            opcode++;
        }
 
    } else {
        TTAMachine::HWOperation* hwop = adfFU_->operation(0);
        operations_.emplace_back(hwop->name());
        fu_.appendToHeader("  " + hwop->name() + " : 0");
    }
    fu_.appendToHeader("");
}

References TTAMachine::HWOperation::name().

Referenced by implement().

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createImplementationFiles()

void FUGen::createImplementationFiles ( )

private

Definition at line 290 of file FUGen.cc.

                                 {
    if (options_.language == ProGe::HDL::VHDL) {
        Path dir = Path(options_.outputDirectory) / "vhdl";
        FileSystem::createDirectory(dir.string());
        Path file = dir / (fu_.name() + ".vhd");
        std::ofstream ofs(file);
        fu_.implement(ofs, Language::VHDL);
    } else if (options_.language == ProGe::HDL::Verilog) {
        Path dir = Path(options_.outputDirectory) / "verilog";
        FileSystem::createDirectory(dir.string());
        Path file = dir / (fu_.name() + ".v");
        std::ofstream ofs(file);
        fu_.implement(ofs, Language::Verilog);
    }
 
    // Copy synthesis files and simulation models.
    for (auto&& opInfo : fug_.operations()) {
        std::string hdb = opInfo.hdb;
        hdb = findAbsolutePath(hdb);
        HDB::CachedHDBManager& manager = HDB::CachedHDBManager::instance(hdb);
        HDB::OperationImplementation opImpl =
            manager.OperationImplementationByID(opInfo.id);
        for (auto&& r : opImpl.resources) {
            for (size_t i = 0; i < r.simFiles.size(); ++i) {
                copyImplementation(r.simFiles[i], r.simFormats[i], false);
            }
            for (size_t i = 0; i < r.synFiles.size(); ++i) {
                copyImplementation(r.synFiles[i], r.synFormats[i], true);
            }
        }
    }
}

References FileSystem::createDirectory(), HDB::CachedHDBManager::instance(), HDB::HDBManager::OperationImplementationByID(), HDB::OperationImplementation::resources, HDLGenerator::Verilog, ProGe::Verilog, HDLGenerator::VHDL, and ProGe::VHDL.

Referenced by implement().

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createMandatoryPorts()

void FUGen::createMandatoryPorts ( )

private

Definition at line 327 of file FUGen.cc.

                            {
    std::string resetPort;
    if (ProGeTools::findInOptionList("active low reset", globalOptions_)) {
        resetPort = "rstx";
    } else {
        resetPort = "rst";
    }
 
    fu_ << InPort("clk") << InPort(resetPort) << InPort("glock_in")
        << OutPort("glockreq_out");
 
    if (adfFU_->operationCount() > 1) {
        fu_ << InPort("operation_in", opcodeWidth_, WireType::Vector);
    }
 
    // operand ports.
    for (int i = 0; i < adfFU_->portCount(); ++i) {
        TTAMachine::FUPort* adfPort =
            static_cast<TTAMachine::FUPort*>(adfFU_->port(i));
 
        if (adfPort->isInput()) {
            fu_ << InPort(
                "data_" + adfPort->name() + "_in", adfPort->width(),
                WireType::Vector);
            fu_ << InPort("load_" + adfPort->name() + "_in");
        } else {
            fu_ << OutPort(
                "data_" + adfPort->name() + "_out", adfPort->width(),
                WireType::Vector);
        }
    }
 
    if (addressWidth_ > 0) {
        fu_ << IntegerConstant("addrw_c", addressWidth_);
    }
}

References ProGeTools::findInOptionList(), TTAMachine::Port::isInput(), TTAMachine::Port::name(), HDLGenerator::Vector, and TTAMachine::BaseFUPort::width().

Referenced by implement().

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createOperationResources()

void FUGen::createOperationResources ( )

private

Definition at line 634 of file FUGen.cc.

                                {
    std::map<std::string, int> instantiatedResources;
    for (auto&& rs : baseOperations_) {
        for (auto&& r : rs.second.resources) {
            if (!instantiatedResources.count(r.name)) {
                instantiatedResources[r.name] = 0;
            }
            std::string file = findAbsolutePath(r.ipxact);
            std::string rName = StringTools::stringToLower(r.name);
            int rCount = resourceCount_[rName];
 
            for (int i = instantiatedResources[r.name]; i < rCount; ++i) {
                auto module = ipxact::parseComponent(file);
                Module resource(module, i + 1);
                resource.set_prefix(rName);
                fu_ << resource;
                for (auto&& p : module.ports) {
                    std::string wName = StringTools::stringToLower(
                        rName + "_" + std::to_string(i + 1) + "_" + p.name);
                    if (p.vector) {
                        fu_ << Wire(wName, p.width);
                    } else {
                        fu_ << Wire(wName);
                    }
 
                    if (p.direction == "in") {
                        resourceInputs_.emplace_back(wName);
                    } else {
                        resourceOutputs_.emplace_back(wName);
                    }
                }
            }
            instantiatedResources[r.name] = rCount;
        }
    }
}

References ipxact::parseComponent(), HDLGenerator::Module::set_prefix(), and StringTools::stringToLower().

Referenced by implement().

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createOutputPipeline()

void FUGen::createOutputPipeline ( )

private

Definition at line 1385 of file FUGen.cc.

                            {
    CodeBlock outputPipeline;
    CodeBlock lastStage;
 
    for (int i = 0; i < adfFU_->portCount(); ++i) {
        auto port = adfFU_->port(i);
        int length = pipelineLength_[port->name()];
        int width = port->width();
        if (portDirection_[port->name()] != ProGe::Direction::OUT) {
            continue;
        }
 
        auto inputs = portInputs_.equal_range(port->name());
        for (int cycle = length; cycle >= 0; --cycle) {
            bool cycleActive = false;
 
            std::string nextReg = pipelineName(port->name(), cycle);
            std::string prevReg = pipelineName(port->name(), cycle + 1);
            std::string valid = pipelineValid(port->name(), cycle);
 
            if (cycle == 0) {
                fu_ << Wire(nextReg, width, WireType::Vector);
            } else {
                outputPipeline.append(Assign(valid, BinaryLiteral("1")));
                addRegisterIfMissing(nextReg, width, WireType::Vector);
                addRegisterIfMissing(valid, 1);
            }
 
            // TODO: build a mux if all operations come from the same cycle
            If validOperations(BinaryLiteral("1"), DefaultAssign("dummy"));
            for (auto it = inputs.first; it != inputs.second; ++it) {
                auto connection = it->second;
                if (connection.pipelineStage != cycle) {
                    continue;
                }
 
                Equals triggered(
                    LHSSignal(triggerSignal(connection.sourceCycle)),
                    BinaryLiteral("1"));
                LogicalAnd active(
                    Equals(
                        LHSSignal(opcodeSignal(connection.sourceCycle)),
                        LHSSignal(opcodeConstant(connection.operation))),
                    triggered);
 
                Ext source(
                    operandSignal(connection.operation, connection.operandID),
                    width, connection.operandWidth);
 
                if (cycleActive) {
                    if (operations_.size() == 1) {
                        validOperations.elseIfClause(
                            triggered, Assign(nextReg, source));
                    } else {
                        validOperations.elseIfClause(
                            active, Assign(nextReg, source));
                    }
                } else {
                    if (operations_.size() == 1) {
                        validOperations =
                            If(triggered, Assign(nextReg, source));
                    } else {
                        validOperations = If(active, Assign(nextReg, source));
                    }
                }
                cycleActive = true;
            }
 
            bool skip_last_assign = false;
            // No need for this on first cycle
            if (cycle != length) {
                std::string prevValid =
                    pipelineValid(port->name(), cycle + 1);
 
                Equals isValid(LHSSignal(prevValid), BinaryLiteral("1"));
                if (cycleActive) {
                    validOperations.elseIfClause(
                        isValid, Assign(nextReg, LHSSignal(prevReg)));
                } else {
                    if (cycle == 0) {
                        skip_last_assign = true;
                        lastStage.append(Assign(nextReg, LHSSignal(prevReg)));
                    } else {
                        validOperations =
                            If(isValid, Assign(nextReg, LHSSignal(prevReg)));
                    }
                }
                cycleActive = true;
            }
 
            if (cycle == 0) {
                std::string outReg = nextReg + "_r";
                addRegisterIfMissing(outReg, width, WireType::Vector);
                outputPipeline.append(Assign(outReg, LHSSignal(nextReg)));
 
                Assign finalStep(nextReg, LHSSignal(outReg));
                if (!skip_last_assign) {
                    if (cycleActive) {
                        validOperations.elseClause(finalStep);
                        lastStage.append(validOperations);
                    } else {
                        lastStage.append(finalStep);
                    }
                }
            } else {
                validOperations.elseClause(Assign(valid, BinaryLiteral("0")));
                outputPipeline.append(validOperations);
            }
        }
        lastStage.append(Assign(
            "data_" + port->name() + "_out",
            LHSSignal(pipelineName(port->name(), 0))));
    }
 
    Synchronous sync("output_pipeline_sp");
    sync << If(
        Equals(LHSSignal("glock_in"), BinaryLiteral("0")), outputPipeline);
    behaviour_ << sync;
 
    Asynchronous async("output_pipeline_cp");
    async << lastStage;
    behaviour_ << async;
}

References HDLGenerator::CodeBlock::append(), HDLGenerator::If::elseClause(), HDLGenerator::If::elseIfClause(), HDB::OUT, HDLGenerator::Vector, and HDLGenerator::Generatable::width().

Referenced by implement().

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createPortPipeline()

void FUGen::createPortPipeline ( )

private

Definition at line 1317 of file FUGen.cc.

                          {
    CodeBlock pipelineAssignments;
    CodeBlock firstStage;
 
    // Pipeline for opcode and trigger
    // TODO: This might generate some unnecessary registers for some FUs,
    // but these should be removed by the synthesis tool
    for (int i = 0; i < maxLatency_; ++i) {
        if (operations_.size() > 1) {
            std::string prevOpcode = opcodeSignal(i);
            std::string nextOpcode = opcodeSignal(i + 1);
            addRegisterIfMissing(nextOpcode, opcodeWidth_, WireType::Vector);
            if (i == 0) {
                firstStage.append(Assign(nextOpcode, LHSSignal(prevOpcode)));
            } else {
                pipelineAssignments.append(
                    Assign(nextOpcode, LHSSignal(prevOpcode)));
            }
        }
        std::string prevTrigger = triggerSignal(i);
        std::string nextTrigger = triggerSignal(i + 1);
        addRegisterIfMissing(nextTrigger, 1);
        pipelineAssignments.append(
            Assign(nextTrigger, LHSSignal(prevTrigger)));
    }
 
    // Pipelines for operand data
    for (int i = 0; i < adfFU_->portCount(); ++i) {
        auto port = adfFU_->port(i);
        int length = pipelineLength_[port->name()];
        int width = port->width();
        if (portDirection_[port->name()] != ProGe::Direction::IN) {
            continue;
        }
 
        for (int i = 0; i < length; ++i) {
            std::string prevReg = pipelineName(port->name(), i);
            std::string nextReg = pipelineName(port->name(), i + 1);
            addRegisterIfMissing(nextReg, width, WireType::Vector);
            if (i == 0) {
                firstStage.append(Assign(nextReg, LHSSignal(prevReg)));
            } else {
                pipelineAssignments.append(
                    Assign(nextReg, LHSSignal(prevReg)));
            }
        }
    }
 
    If operationTrigger(
        Equals(LHSSignal(triggerSignal(0)), BinaryLiteral("1")), firstStage);
    pipelineAssignments.append(operationTrigger);
    If glock_low(
        Equals(LHSSignal("glock_in"), BinaryLiteral("0")),
        pipelineAssignments);
    Synchronous pipeline("input_pipeline_sp");
    pipeline << glock_low;
    behaviour_ << pipeline;
}

References HDLGenerator::CodeBlock::append(), HDB::IN, and HDLGenerator::Vector.

Referenced by implement().

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createShadowRegisters()

void FUGen::createShadowRegisters ( )

private

Definition at line 1243 of file FUGen.cc.

                             {
    std::vector<std::string> inOperands;
    std::unordered_set<std::string> registeredInOperands;
    std::unordered_map<std::string, std::string> currentName;
    std::unordered_map<std::string, int> portWidth;
 
    for (int i = 0; i < adfFU_->portCount(); ++i) {
        TTAMachine::FUPort* adfPort =
            static_cast<TTAMachine::FUPort*>(adfFU_->port(i));
        portWidth[adfPort->name()] = adfPort->width();
 
        if (adfPort->isInput()) {
            currentName[adfPort->name()] = "data_" + adfPort->name() + "_in";
 
            if (adfPort->isTriggering()) {
                triggerPort_ = adfPort->name();
            }
 
            inOperands.emplace_back(adfPort->name());
            if (!adfPort->noRegister()) {
                registeredInOperands.emplace(adfPort->name());
            }
 
            std::string name = pipelineName(adfPort->name(), 0);
            fu_ << Wire(name, adfPort->width());
        } else {
            currentName[adfPort->name()] = "data_" + adfPort->name() + "_out";
        }
    }
 
    if (ProGeTools::findInOptionList(fug_.name(), options_.fuIcGateList)) {
        for (auto&& p : inOperands) {
            std::string newName = "data_" + p + "_gated";
            auto gate = LHSSignal(currentName[p]) &
                        Sext("load_" + p + "_in", portWidth[p], 1);
            behaviour_ << Assign(newName, gate);
            currentName[p] = newName;
            fu_ << Wire(newName, portWidth[p]);
        }
    }
 
    for (auto&& p : inOperands) {
        std::string dataPort = currentName[p];
        std::string output = pipelineName(p, 0);
        if (p != triggerPort_ &&
            registeredInOperands.find(p) != registeredInOperands.end()) {
            std::string loadPort = "load_" + p + "_in";
            std::string shadowReg = "shadow_" + p + "_r";
 
            fu_ << Register(shadowReg, portWidth[p], ResetOption::Optional);
 
            auto noLock = Equals(LHSSignal("glock_in"), BinaryLiteral("0"));
            auto portLoad = Equals(LHSSignal(loadPort), BinaryLiteral("1"));
            If iffi(
                noLock && portLoad, Assign(shadowReg, LHSSignal(dataPort)));
 
            behaviour_ << (Synchronous("shadow_" + p + "_sp") << iffi);
 
            auto triggerLoad = Equals(
                LHSSignal("load_" + triggerPort_ + "_in"),
                BinaryLiteral("1"));
            If cpIf(
                triggerLoad && portLoad,
                Assign(output, LHSSignal("data_" + p + "_in")));
            cpIf.elseClause(Assign(output, LHSSignal(shadowReg)));
 
            behaviour_ << (Asynchronous("shadow_" + p + "_cp") << cpIf);
        } else {
            behaviour_ << Assign(output, LHSSignal(dataPort));
        }
    }
}

References HDLGenerator::If::elseClause(), ProGeTools::findInOptionList(), TTAMachine::Port::isInput(), TTAMachine::FUPort::isTriggering(), TTAMachine::Port::name(), TTAMachine::FUPort::noRegister(), HDLGenerator::Optional, and TTAMachine::BaseFUPort::width().

Referenced by implement().

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DAGNodeOperandWidth()

int FUGen::DAGNodeOperandWidth ( OperationDAGNode &  node, int  id, OperationDAG *  dag  )

private

Definition at line 201 of file FUGen.cc.

                                                       {
    auto operation = dynamic_cast<OperationNode*>(&node);
    auto terminal = dynamic_cast<TerminalNode*>(&node);
    auto constant = dynamic_cast<ConstantNode*>(&node);
 
    OperationPool opPool;
    std::string opName;
    if (operation) {
        opName = operation->referencedOperation().name();
    } else if (terminal) {
        opName = dag->operation().name();
    } else if (constant) {
        return MathTools::requiredBitsSigned(constant->value());
    } else {
        assert(false && "Shouldn't be possible to get here.");
    }
 
    opName = StringTools::stringToLower(opName);
    Operation& op = opPool.operation(opName.c_str());
    return op.operand(id).width();
}

References assert, OperationPimpl::name(), Operation::operand(), OperationPool::operation(), OperationDAG::operation(), MathTools::requiredBitsSigned(), StringTools::stringToLower(), and Operand::width().

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finalizeHDL()

void FUGen::finalizeHDL ( )

private

Definition at line 889 of file FUGen.cc.

                   {
    // Create lock request wires
    if (useGlockRequest_) {
        fu_ << Wire("glockreq");
        behaviour_ << Assign("glockreq_out", LHSSignal("glockreq"));
    } else {
        behaviour_ << Assign("glockreq_out", BinaryLiteral("0"));
    }
 
    // Finalize and set global options.
    fu_ << behaviour_;
    for (auto&& option : globalOptions_) {
        fu_ << Option(option);
    }
}

Referenced by implement().

findAbsolutePath()

std::string FUGen::findAbsolutePath ( std::string  file )

private

Searches for file in TCE folders and makes the path absolute.

Definition at line 101 of file FUGen.cc.

                                      {
    if (file.length() > 4 && file.substr(0, 4) == "tce:") {
        file = file.substr(4);
    }
    std::vector<std::string> paths = Environment::hdbPaths();
    for (auto file : options_.hdbList) {
        paths.emplace_back(FileSystem::directoryOfPath(file));
    }
    return FileSystem::findFileInSearchPaths(paths, file);
}

References FileSystem::directoryOfPath(), FileSystem::findFileInSearchPaths(), and Environment::hdbPaths().

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hasToken()

bool FUGen::hasToken ( std::string  line, std::string  token  )

private

Definition at line 61 of file FUGen.cc.

                                               {
    auto regex = std::regex("\\b" + token + "\\b");
    return std::regex_search(line, regex);
}

implement()

void FUGen::implement ( const ProGeOptions &  options, std::vector< std::string >  globalOptions, const std::vector< IDF::FUGenerated > &  generatetFUs, const TTAMachine::Machine &  machine, ProGe::NetlistBlock *  core  )

static

Generate all FUGen FUs.

Definition at line 1515 of file FUGen.cc.

                                                               {
    // Generate FU innards.
    for (auto fug : generatetFUs) {
        FUGen fugen(options, globalOptions, fug, machine, core);
 
        // Some repetition to have named FUs override an "all"
        // e.g. --fu-front-register=all --fu-back-register=lsu
        if (ProGeTools::findInOptionList(
                fug.name(), options.fuFrontRegistered, false)) {
            fugen.frontRegistered_ = true;
        } else if (ProGeTools::findInOptionList(
                       fug.name(), options.fuMiddleRegistered, false)) {
            fugen.middleRegistered_ = true;
        } else if (ProGeTools::findInOptionList(
                       fug.name(), options.fuBackRegistered, false)) {
            fugen.backRegistered_ = true;
        } else if (ProGeTools::findInOptionList(
                       fug.name(), options.fuFrontRegistered)) {
            fugen.frontRegistered_ = true;
        } else if (ProGeTools::findInOptionList(
                       fug.name(), options.fuMiddleRegistered)) {
            fugen.middleRegistered_ = true;
        } else {  // Default to back-register
            fugen.backRegistered_ = true;
        }
 
        fugen.createFUHeaderComment();
        fugen.checkForValidity();
 
        fugen.parseOperations();
        fugen.scheduleOperations();
        fugen.createMandatoryPorts();
        fugen.createExternalInterfaces(!options.integratorName.empty());
        fugen.createOperationResources();
 
        fugen.createShadowRegisters();
        fugen.createPortPipeline();
        fugen.buildOperations();
        fugen.createOutputPipeline();
 
        fugen.finalizeHDL();
        fugen.createImplementationFiles();
    }
}

References backRegistered_, buildOperations(), checkForValidity(), createExternalInterfaces(), createFUHeaderComment(), createImplementationFiles(), createMandatoryPorts(), createOperationResources(), createOutputPipeline(), createPortPipeline(), createShadowRegisters(), finalizeHDL(), ProGeTools::findInOptionList(), frontRegistered_, machine, middleRegistered_, options, parseOperations(), and scheduleOperations().

Referenced by ProGe::ProcessorGenerator::generateProcessor().

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inferLSUSignal()

ProGe::Signal FUGen::inferLSUSignal ( const std::string &  portName ) const

private

(Ugly) heuristics for mapping FUGen generated LSU signal types

Parameters

portName

Name of the port

Returns

SignalType

Definition at line 542 of file FUGen.cc.

                                                     {
    size_t pos = 0;
    using SigT = ProGe::SignalType;
    if (((pos = portName.find("avalid")) != std::string::npos)) {
        return SigT::AVALID;
    } else if (((pos = portName.find("aready")) != std::string::npos)) {
        return SigT::AREADY;
    } else if (((pos = portName.find("aaddr")) != std::string::npos)) {
        return SigT::AADDR;
    } else if (((pos = portName.find("awren")) != std::string::npos)) {
        return SigT::AWREN;
    } else if (((pos = portName.find("astrb")) != std::string::npos)) {
        return SigT::ASTRB;
    } else if (((pos = portName.find("rvalid")) != std::string::npos)) {
        return SigT::RVALID;
    } else if (((pos = portName.find("rready")) != std::string::npos)) {
        return SigT::RREADY;
    } else if (((pos = portName.find("rdata")) != std::string::npos)) {
        return SigT::RDATA;
    } else if (((pos = portName.find("adata")) != std::string::npos)) {
        return SigT::ADATA;
    }
    return SigT::UNDEFINED;
}

isLSUDataPort()

bool FUGen::isLSUDataPort ( const std::string &  portName )

private

(Ugly) heuristics for identifying an LSU data memory port.

The identification is made by partial match of the port's name.

Parameters

portName

The port name given in HDB.

Returns

True if the port is LSU data memory port.

Definition at line 516 of file FUGen.cc.

                                              {
    if (!adfFU_->hasAddressSpace()) {
        return false;
    }
 
    static const std::set<std::string> magicWords{
        "avalid", "aready", "aaddr", "awren", "astrb",
        "rvalid", "rready", "rdata", "adata"};
 
    for (auto magicWord : magicWords) {
        if (portName.find(magicWord) != std::string::npos) {
            //Assume the FU is an LSU
            isLSU_ = true;
            return true;
        }
    }
 
    return false;
}

opcodeConstant()

std::string FUGen::opcodeConstant ( std::string  operation )

private

Definition at line 131 of file FUGen.cc.

                                         {
    return "op_" + operation + "_c";
}

opcodeSignal()

std::string FUGen::opcodeSignal ( int  stage )

private

Definition at line 113 of file FUGen.cc.

                             {
    if (stage == 0) {
        return "operation_in";
    } else {
        return "operation_" + std::to_string(stage) + "_r";
    }
}

operandPlaceholder()

std::string FUGen::operandPlaceholder ( int  id )

private

Definition at line 141 of file FUGen.cc.

                                {
    return "op" + std::to_string(id);
}

operandSignal()

std::string FUGen::operandSignal ( std::string  operation, int  id  )

private

Definition at line 136 of file FUGen.cc.

                                                {
    return operation + "_op" + std::to_string(id);
}

operator=()

FUGen& FUGen::operator= ( const FUGen &  )

delete

parseOperations()

void FUGen::parseOperations ( )

private

Definition at line 906 of file FUGen.cc.

                       {
    OperationPool opPool;
    std::vector<std::string> dagOperations;
 
    for (auto&& op : fug_.operations()) {
        BaseOperation opInfo;
        opInfo.name = op.operationName;
        opInfo.latency = op.latency;
 
        std::string opHDB = findAbsolutePath(op.hdb);
        HDB::CachedHDBManager& manager =
            HDB::CachedHDBManager::instance(opHDB);
        HDB::OperationImplementation opImpl =
            manager.OperationImplementationByID(op.id);
 
        std::string implFile;
        if (options_.language == ProGe::HDL::VHDL) {
            opInfo.variables = opImpl.vhdlVariables;
            opInfo.globalsignals = opImpl.vhdlGlobalSignals;
            opInfo.implementation = readFile(opImpl.implFileVhdl);
            opInfo.initial = readFile(opImpl.initialImplFileVhdl);
            opInfo.postOp = readFile(opImpl.postOpImplFileVhdl);
        } else {
            if (opImpl.implFileVerilog == "") {
                const std::string msg = 
                "Cannot generate operation \"" + opInfo.name +
                "\" due to missing verilog operation implementation";
                throw std::runtime_error(msg);
            }
            opInfo.variables = opImpl.verilogVariables;
            opInfo.globalsignals = opImpl.verilogGlobalSignals;
            opInfo.implementation = readFile(opImpl.implFileVerilog);
            opInfo.initial = readFile(opImpl.initialImplFileVerilog);
            opInfo.postOp = readFile(opImpl.postOpImplFileVerilog);
        }
        opInfo.resources = opImpl.resources;
 
        implLatency_[opInfo.name] = op.latency;
 
        baseOperations_.emplace(opInfo.name, opInfo);
 
        std::string ifPath = opImpl.absBusDefFile;
        if (!ifPath.empty()) {
            extIfaces_.insert(findAbsolutePath(ifPath));
        }
    }
 
    maxLatency_ = 0;
    minLatency_ = INT_MAX;
    for (auto&& op : operations_) {
        TTAMachine::HWOperation* hwOp = adfFU_->operation(op);
        int hwOpOperands = hwOp->operandCount();
        OperationPool opPool;
 
        for (int operand = 0; operand < hwOpOperands; ++operand) {
            TTAMachine::FUPort* fuPort = hwOp->port(operand + 1);
 
            if (fuPort->isOutput()) {
                std::string portName = fuPort->name();
                int latency = hwOp->latency(operand + 1);
 
                auto search = operationCycles_.find(op);
                if (search != operationCycles_.end()) {
                    operationCycles_[op] = std::max(search->second, latency);
                } else {
                    operationCycles_[op] = latency;
                }
                maxLatency_ = std::max(maxLatency_, latency);
                minLatency_ = std::min(minLatency_, latency);
            }
        }
 
        if (baseOperations_.find(op) == baseOperations_.end()) {
            dagOperations.emplace_back(op);
        }
    }
 
    for (auto&& op : dagOperations) {
        int dagCount;
        {
            OperationPool opPool;
            Operation& osalOp = opPool.operation(op.c_str());
            dagCount = osalOp.dagCount();
        }
 
        if (dagCount < 1) {
            throw std::runtime_error(op + " has no dags to implement.");
        }
 
        bool implementable = false;
        for (int i = 0; i < dagCount; ++i) {
            OperationDAG* dagPtr;
            {
                OperationPool opPool;
                OperationIndex& index = opPool.index();
                Operation* osalOp = index.effectiveOperation(op);
                dagPtr = &osalOp->dag(i);
            }
 
            if (!ProGeTools::canGenerateFromDAG(
                    *dagPtr, fug_.operations(), nullptr)) {
                continue;
            } else {
                implementable = true;
                implementapleDAGs_[op] = dagPtr;
                implLatency_[op] =
                    ProGeTools::dagLatency(*dagPtr, implLatency_);
                break;
            }
        }
 
        if (!implementable) {
            throw std::runtime_error(op + " has no valid dags to implement.");
        }
    }
}

References HDB::OperationImplementation::absBusDefFile, ProGeTools::canGenerateFromDAG(), Operation::dag(), Operation::dagCount(), ProGeTools::dagLatency(), OperationIndex::effectiveOperation(), FUGen::BaseOperation::globalsignals, FUGen::BaseOperation::implementation, HDB::OperationImplementation::implFileVerilog, HDB::OperationImplementation::implFileVhdl, OperationPool::index(), FUGen::BaseOperation::initial, HDB::OperationImplementation::initialImplFileVerilog, HDB::OperationImplementation::initialImplFileVhdl, HDB::CachedHDBManager::instance(), TTAMachine::Port::isOutput(), TTAMachine::HWOperation::latency(), FUGen::BaseOperation::latency, TTAMachine::Port::name(), FUGen::BaseOperation::name, TTAMachine::HWOperation::operandCount(), OperationPool::operation(), HDB::HDBManager::OperationImplementationByID(), TTAMachine::HWOperation::port(), FUGen::BaseOperation::postOp, HDB::OperationImplementation::postOpImplFileVerilog, HDB::OperationImplementation::postOpImplFileVhdl, HDB::OperationImplementation::resources, FUGen::BaseOperation::resources, FUGen::BaseOperation::variables, HDB::OperationImplementation::verilogGlobalSignals, HDB::OperationImplementation::verilogVariables, ProGe::VHDL, HDB::OperationImplementation::vhdlGlobalSignals, and HDB::OperationImplementation::vhdlVariables.

Referenced by implement().

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pipelineName()

std::string FUGen::pipelineName ( std::string  port, int  cycle  )

private

Definition at line 146 of file FUGen.cc.

                                             {
    if (cycle == 0) {
        return "data_" + port;
    } else {
        return "data_" + port + "_" + std::to_string(cycle) + "_r";
    }
}

pipelineValid()

std::string FUGen::pipelineValid ( std::string  port, int  cycle  )

private

Definition at line 155 of file FUGen.cc.

                                              {
    return "data_" + port + "_" + std::to_string(cycle) + "_valid_r";
}

prepareSnippet()

void FUGen::prepareSnippet ( std::string  name, std::deque< std::string >  statements, HDLGenerator::CodeBlock &  sink, std::set< std::string > &  addedStatements  )

private

Definition at line 854 of file FUGen.cc.

                                        {
    std::deque<std::string> snippet;
    std::set<std::string> lines;
    for (std::string line : statements) {
        std::string replaced = StringTools::stringToLower(line);
        for (Replace rep : replacesPerOp_[name]) {
            replaced = replaceToken(replaced, rep);
        }
 
        // Cosmetic improvement: do not repeat statements in the same context
        if (addedStatements.count(replaced)) {
            continue;
        }
        lines.insert(replaced);
 
        snippet.push_back(replaced);
 
        if (hasToken(line, "glockreq")) {
            useGlockRequest_ = true;
        }
        if (hasToken(line, "glock")) {
            useGlock_ = true;
        }
    }
 
    for (std::string line : lines) {
        addedStatements.insert(line);
    }
 
    sink.append(HDLOperation(name, snippet, selectedLanguage()));
}

References HDLGenerator::CodeBlock::append(), and StringTools::stringToLower().

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readFile()

std::deque< std::string > FUGen::readFile ( std::string  filename )

private

Definition at line 82 of file FUGen.cc.

                                  {
    std::deque<std::string> file;
    // replace temps in operation implmentations and keep track of
    // read temps.
    if (filename == "") {
        return file;
    }
 
    std::ifstream implStream(findAbsolutePath(filename));
    for (std::string line; std::getline(implStream, line);) {
        file.emplace_back(StringTools::stringToLower(line));
    }
    return file;
}

References StringTools::stringToLower().

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readImplementation()

void FUGen::readImplementation ( std::string  filename, std::string  opName, std::deque< std::string > &  sink  )

private

Definition at line 492 of file FUGen.cc.

                                                                     {
    // replace temps in operation implmentations and keep track of
    // read temps.
    std::ifstream implStream(findAbsolutePath(filename));
    for (std::string line; std::getline(implStream, line);) {
        line = StringTools::stringToLower(line);
        for (auto&& p : replacesPerOp_[opName]) {
            line = replaceToken(line, p);
        }
 
        sink.emplace_back(line);
    }
}

References StringTools::stringToLower().

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replaceToken()

std::string FUGen::replaceToken ( std::string  line, Replace  replace  )

private

Definition at line 67 of file FUGen.cc.

                                                   {
    auto regex = std::regex("\\b" + replace.first + "\\b");
    return std::regex_replace(line, regex, replace.second);
}

scheduleOperations()

void FUGen::scheduleOperations ( )

private

Definition at line 1064 of file FUGen.cc.

                          {
    std::set<std::string> instantiatedWires;
    for (auto&& op : operations_) {
        OperationSchedule schedule;
        schedule.baseOp = op;
 
        if (frontRegistered_) {
            schedule.initialCycle = operationCycles_[op] - implLatency_[op];
            schedule.finalCycle = operationCycles_[op];
        } else if (middleRegistered_) {
            schedule.initialCycle =
                operationCycles_[op] - implLatency_[op] - 1;
            schedule.finalCycle = schedule.initialCycle + implLatency_[op];
        } else {  // Back-registered
            schedule.initialCycle = 0;
            schedule.finalCycle = implLatency_[op];
        }
        assert(
            schedule.initialCycle >= 0 &&
            "Failure likely due to mis-selected operation implementation");
 
        OperationPool opPool;
        Operation& osalOp = opPool.operation(op.c_str());
        TTAMachine::HWOperation* hwOp = adfFU_->operation(op);
        for (int i = 1; i <= hwOp->operandCount(); ++i) {
            Operand& osalOperand = osalOp.operand(i);
            TTAMachine::FUPort* fuPort = hwOp->port(i);
            std::string port = fuPort->name();
            int width = osalOperand.width();
            int accessCycle;
            ProGe::Direction dir;
 
            OperandConnection oper = {
                i, fuPort->width(), width,
                pipelineName(port, schedule.initialCycle), false};
            if (osalOperand.isInput()) {
                accessCycle = schedule.initialCycle;
                schedule.operands.push_back(oper);
                dir = ProGe::Direction::IN;
            } else {
                accessCycle = operationCycles_[op] - schedule.finalCycle;
                schedule.results.insert(i);
                dir = ProGe::Direction::OUT;
                OutputConnection out = {
                    width, i, schedule.finalCycle, accessCycle, op};
                portInputs_.emplace(port, out);
            }
 
            assert(
                accessCycle >= 0 &&
                "Failure likely due to mis-selected operation "
                "implementation");
 
            std::string newWire = operandSignal(op, i);
            if (!instantiatedWires.count(newWire)) {
                fu_ << Wire(newWire, width);
                instantiatedWires.insert(newWire);
            }
 
            if (pipelineLength_.find(port) == pipelineLength_.end()) {
                pipelineLength_[port] = accessCycle;
            } else {
                pipelineLength_[port] =
                    std::max(accessCycle, pipelineLength_[port]);
            }
 
            if (portDirection_.find(port) == portDirection_.end()) {
                portDirection_[port] = dir;
            } else {
                if (portDirection_[port] != dir) {
                    throw std::runtime_error(
                        "Unsupported bidirectional port " + port +
                        ", aborting.");
                }
            }
        }
 
        if (baseOperations_.find(op) != baseOperations_.end()) {
            // No need to arbitrate between suboperations here,
            // just use the first resource
            for (auto&& res : baseOperations_[op].resources) {
                std::string resName = StringTools::stringToLower(res.name);
                schedule.resourceOffsets[resName] = 0;
                resourceCount_[res.name] =
                    std::max(resourceCount_[res.name], res.count);
            }
        } else {
            assert(implementapleDAGs_.find(op) != implementapleDAGs_.end());
            auto dag = implementapleDAGs_[op];
            std::unordered_map<std::string, int> dagResourceCount;
 
            for (int n = 0; n < dag->nodeCount(); ++n) {
                OperationSchedule subopSchedule;
                OperationDAGNode& node = dag->node(n);
 
                OperationNode* operationNode =
                    dynamic_cast<OperationNode*>(&node);
 
                if (!operationNode) {
                    continue;
                }
 
                std::string subOp =
                    operationNode->referencedOperation().name();
                subOp = StringTools::stringToLower(subOp);
 
                std::string name = subOpName(operationNode);
                schedule.subOperations.push_back(name);
                subopSchedule.baseOp = subOp;
                // Start counting subopcycles from the upper op's initCycle.
                subopSchedule.initialCycle =
                    schedule.initialCycle +
                    ProGeTools::maxLatencyToNode(
                        *dag, node, implLatency_, false);
                subopSchedule.finalCycle =
                    subopSchedule.initialCycle + implLatency_[subOp];
 
                for (auto&& input : dag->inEdges(node)) {
                    int dstID = input->dstOperand();
                    int width = DAGNodeOperandWidth(
                        dag->headNode(*input), dstID, dag);
 
                    std::string newWire = operandSignal(name, dstID);
                    if (!instantiatedWires.count(newWire)) {
                        fu_ << Wire(newWire, width);
                        instantiatedWires.insert(newWire);
                    }
 
                    subopSchedule.operands.push_back(
                        subOpConnection(dag, input, false));
                }
 
                for (auto&& output : dag->outEdges(node)) {
                    int srcID = output->srcOperand();
                    int width = DAGNodeOperandWidth(
                        dag->tailNode(*output), srcID, dag);
 
                    std::string newWire = operandSignal(name, srcID);
                    if (!instantiatedWires.count(newWire)) {
                        fu_ << Wire(newWire, width);
                        instantiatedWires.insert(newWire);
                    }
 
                    subopSchedule.results.insert(srcID);
 
                    auto terminal =
                        dynamic_cast<TerminalNode*>(&dag->headNode(*output));
 
                    if (terminal) {
                        schedule.operands.push_back(
                            subOpConnection(dag, output, true));
                    }
                }
 
                // TODO: make sure same resource doesn't get used by different
                // operations on _different_ pipeline cycles
                for (auto&& r : baseOperations_[subOp].resources) {
                    std::string resName = StringTools::stringToLower(r.name);
                    if (!dagResourceCount.count(resName)) {
                        dagResourceCount[resName] = 0;
                    }
                    subopSchedule.resourceOffsets[resName] =
                        dagResourceCount[resName];
                    dagResourceCount[resName] += r.count;
                }
 
                scheduledOperations_[name] = subopSchedule;
            }
 
            for (auto&& d : dagResourceCount) {
                resourceCount_[d.first] =
                    std::max(resourceCount_[d.first], d.second);
            }
        }
        scheduledOperations_[op] = schedule;
    }
}

References assert, FUGen::OperationSchedule::baseOp, FUGen::OperationSchedule::finalCycle, HDB::IN, FUGen::OperationSchedule::initialCycle, Operand::isInput(), ProGeTools::maxLatencyToNode(), TTAMachine::Port::name(), Operation::name(), Operation::operand(), TTAMachine::HWOperation::operandCount(), FUGen::OperationSchedule::operands, OperationPool::operation(), HDB::OUT, TTAMachine::HWOperation::port(), OperationNode::referencedOperation(), FUGen::OperationSchedule::resourceOffsets, FUGen::OperationSchedule::results, StringTools::stringToLower(), FUGen::OperationSchedule::subOperations, TTAMachine::BaseFUPort::width(), and Operand::width().

Referenced by implement().

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selectedLanguage()

Language FUGen::selectedLanguage ( )

private

Definition at line 73 of file FUGen.cc.

                        {
    if (options_.language == ProGe::HDL::VHDL) {
        return Language::VHDL;
    } else {
        return Language::Verilog;
    }
}

References HDLGenerator::Verilog, HDLGenerator::VHDL, and ProGe::VHDL.

subOpConnection()

FUGen::OperandConnection FUGen::subOpConnection ( OperationDAG *  dag, OperationDAGEdge *  edge, bool  isOutput  )

private

Definition at line 1024 of file FUGen.cc.

                                                              {
    OperationDAGNode& srcNode = dag->tailNode(*edge);
    int srcID = edge->srcOperand();
    int srcWidth = DAGNodeOperandWidth(srcNode, srcID, dag);
 
    OperationDAGNode& dstNode = dag->headNode(*edge);
    int dstID = edge->dstOperand();
    int dstWidth = DAGNodeOperandWidth(dstNode, dstID, dag);
    auto dstTerminal = dynamic_cast<TerminalNode*>(&dstNode);
    if (dstTerminal) {
        dstID = dstTerminal->operandIndex();
    }
 
    auto operation = dynamic_cast<OperationNode*>(&srcNode);
    auto terminal = dynamic_cast<TerminalNode*>(&srcNode);
    auto constant = dynamic_cast<ConstantNode*>(&srcNode);
 
    std::string signalName;
    if (operation) {
        std::string srcOp = subOpName(operation);
        srcOp = StringTools::stringToLower(srcOp);
        signalName = operandSignal(srcOp, srcID);
    } else if (terminal) {
        std::string srcOp = dag->operation().name();
        srcOp = StringTools::stringToLower(srcOp);
        srcID = terminal->operandIndex();
        signalName = operandSignal(srcOp, srcID);
    } else if (constant) {
        signalName = constantName(constant, dag);
    } else {
        assert(false && "It shouldn't be possible to get here.");
    }
 
    FUGen::OperandConnection conn = {
        dstID, srcWidth, dstWidth, signalName, isOutput};
    return conn;
}

References assert, OperationDAGEdge::dstOperand(), BoostGraph< GraphNode, GraphEdge >::headNode(), OperationPimpl::name(), TerminalNode::operandIndex(), OperationDAG::operation(), OperationDAGEdge::srcOperand(), StringTools::stringToLower(), and BoostGraph< GraphNode, GraphEdge >::tailNode().

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subOpName()

std::string FUGen::subOpName ( OperationNode *  node )

private

Definition at line 160 of file FUGen.cc.

                                    {
    int id;
    std::string op = node->referencedOperation().name();
    op = StringTools::stringToLower(op);
    if (nodeImplementations_.count(node->nodeID())) {
        id = nodeImplementations_[node->nodeID()];
    } else {
        if (!subOpCount_.count(op)) {
            subOpCount_[op] = 0;
        }
        id = subOpCount_[op];
        subOpCount_[op] += 1;
        nodeImplementations_[node->nodeID()] = id;
    }
    return "subop_" + op + "_" + std::to_string(id);
}

References Operation::name(), GraphNode::nodeID(), OperationNode::referencedOperation(), and StringTools::stringToLower().

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triggerSignal()

std::string FUGen::triggerSignal ( int  stage )

private

Definition at line 122 of file FUGen.cc.

                              {
    if (stage == 0) {
        return "load_" + triggerPort_ + "_in";
    } else {
        return "optrig_" + std::to_string(stage) + "_r";
    }
}

Member Data Documentation

addressWidth_

int FUGen::addressWidth_ = 0

private

Definition at line 260 of file FUGen.hh.

Referenced by FUGen().

adfFU_

TTAMachine::FunctionUnit* FUGen::adfFU_

private

Definition at line 211 of file FUGen.hh.

Referenced by FUGen().

backRegistered_

bool FUGen::backRegistered_ = false

private

Definition at line 259 of file FUGen.hh.

Referenced by implement().

baseOperations_

std::unordered_map<std::string, BaseOperation> FUGen::baseOperations_

private

Definition at line 220 of file FUGen.hh.

behaviour_

HDLGenerator::Behaviour FUGen::behaviour_

private

Definition at line 256 of file FUGen.hh.

core_

ProGe::NetlistBlock* FUGen::core_

private

Definition at line 208 of file FUGen.hh.

Referenced by FUGen().

dagConstantCount_

std::unordered_map<std::string, int> FUGen::dagConstantCount_

private

Definition at line 227 of file FUGen.hh.

dagConstants_

std::unordered_map<int, DAGConstant> FUGen::dagConstants_

private

Definition at line 239 of file FUGen.hh.

extIfaces_

std::unordered_set<std::string> FUGen::extIfaces_

private

Definition at line 244 of file FUGen.hh.

extInputs_

std::unordered_set<std::string> FUGen::extInputs_

private

Definition at line 246 of file FUGen.hh.

extOutputs_

std::set<std::pair<std::string, std::string> > FUGen::extOutputs_

private

Definition at line 245 of file FUGen.hh.

frontRegistered_

bool FUGen::frontRegistered_ = false

private

Definition at line 257 of file FUGen.hh.

Referenced by implement().

fu_

HDLGenerator::Module FUGen::fu_

private

Definition at line 210 of file FUGen.hh.

fug_

IDF::FUGenerated& FUGen::fug_

private

Definition at line 207 of file FUGen.hh.

globalOptions_

std::vector<std::string> FUGen::globalOptions_

private

Definition at line 205 of file FUGen.hh.

implementapleDAGs_

std::unordered_map<std::string, OperationDAG*> FUGen::implementapleDAGs_

private

Definition at line 225 of file FUGen.hh.

implLatency_

std::unordered_map<std::string, int> FUGen::implLatency_

private

Definition at line 224 of file FUGen.hh.

isLSU_

bool FUGen::isLSU_ = false

private

Definition at line 261 of file FUGen.hh.

maxLatency_

int FUGen::maxLatency_

private

Definition at line 201 of file FUGen.hh.

middleRegistered_

bool FUGen::middleRegistered_ = false

private

Definition at line 258 of file FUGen.hh.

Referenced by implement().

minLatency_

int FUGen::minLatency_

private

Definition at line 202 of file FUGen.hh.

moduleName_

std::string FUGen::moduleName_

private

Definition at line 216 of file FUGen.hh.

Referenced by FUGen().

netlistBlock_

ProGe::NetlistBlock* FUGen::netlistBlock_

private

Definition at line 217 of file FUGen.hh.

Referenced by FUGen().

nodeImplementations_

std::unordered_map<int, int> FUGen::nodeImplementations_

private

Definition at line 238 of file FUGen.hh.

opcodeWidth_

int FUGen::opcodeWidth_

private

Definition at line 214 of file FUGen.hh.

operationCycles_

std::unordered_map<std::string, int> FUGen::operationCycles_

private

Definition at line 223 of file FUGen.hh.

operations_

std::vector<std::string> FUGen::operations_

private

Definition at line 213 of file FUGen.hh.

options_

const ProGeOptions& FUGen::options_

private

Definition at line 204 of file FUGen.hh.

pipelineLength_

std::unordered_map<std::string, int> FUGen::pipelineLength_

private

Definition at line 233 of file FUGen.hh.

portDirection_

std::unordered_map<std::string, ProGe::Direction> FUGen::portDirection_

private

Definition at line 234 of file FUGen.hh.

portInputs_

std::unordered_multimap<std::string, OutputConnection> FUGen::portInputs_

private

Definition at line 235 of file FUGen.hh.

registers_

std::vector<std::string> FUGen::registers_

private

Definition at line 252 of file FUGen.hh.

renamedGlobalSignals_

std::vector<HDB::Variable> FUGen::renamedGlobalSignals_

private

Definition at line 249 of file FUGen.hh.

renamedVariables_

std::vector<HDB::Variable> FUGen::renamedVariables_

private

Definition at line 248 of file FUGen.hh.

replacesPerOp_

std::unordered_map<std::string, std::vector<Replace> > FUGen::replacesPerOp_

private

Definition at line 222 of file FUGen.hh.

resourceCount_

std::unordered_map<std::string, int> FUGen::resourceCount_

private

Definition at line 230 of file FUGen.hh.

resourceInputs_

std::vector<std::string> FUGen::resourceInputs_

private

Definition at line 241 of file FUGen.hh.

resourceOutputs_

std::vector<std::string> FUGen::resourceOutputs_

private

Definition at line 242 of file FUGen.hh.

scheduledOperations_

std::unordered_map<std::string, OperationSchedule> FUGen::scheduledOperations_

private

Definition at line 221 of file FUGen.hh.

subOpCount_

std::unordered_map<std::string, int> FUGen::subOpCount_

private

Definition at line 226 of file FUGen.hh.

triggerPort_

std::string FUGen::triggerPort_

private

Definition at line 250 of file FUGen.hh.

useGlock_

bool FUGen::useGlock_ = false

private

Definition at line 255 of file FUGen.hh.

useGlockRequest_

bool FUGen::useGlockRequest_ = false

private

Definition at line 254 of file FUGen.hh.

---

The documentation for this class was generated from the following files:

• FUGen.hh
• FUGen.cc