#include <RV32MicroCodeGenerator.hh>

Inheritance diagram for ProGe::RV32MicroCodeGenerator:

Collaboration diagram for ProGe::RV32MicroCodeGenerator:

Public Member Functions
	RV32MicroCodeGenerator (const Machine &machine, const BinaryEncoding &bem)

	~RV32MicroCodeGenerator ()

void	generateRTL (HDLTemplateInstantiator &instantiator, const std::string &fileDst)

void	setBypassInstructionRegister (const bool &value)

Public Member Functions inherited from ProGe::MicroCodeGenerator
	MicroCodeGenerator ()=default

	~MicroCodeGenerator ()=default

Private Member Functions
void	initializeOperations ()

void	findOperationSources ()

void	generateFUTargetProcess (std::ofstream &stream)

void	addRs1ForwardingConditions (std::map< std::string, std::string > ops, std::unordered_map< std::string, InstructionBitVector * >(ProGe::RV32MicroCodeGenerator::instructionFunc)(Port p1, Port *p2) const, std::ofstream &stream) const

void	addRs2ForwardingConditions (std::map< std::string, std::string > ops, std::unordered_map< std::string, InstructionBitVector * >(ProGe::RV32MicroCodeGenerator::instructionFunc)(Port p1, Port *p2) const, std::ofstream &stream) const

std::string	generateOperationLatencyLogic (HDLTemplateInstantiator &instantiator)

std::set< Port * >	operationPorts (const std::unordered_map< std::string, BaseFUPort * > &ports) const

void	validateOperations () const

FunctionUnit *	mapFunctionUnit (const std::string &operation) const

void	addRPorts (const std::string &opName)

void	addIPorts (const std::string &opName)

void	addSPorts (const std::string &opName)

void	addBPorts (const std::string &opName)

void	addUJPorts (const std::string &opName)

void	findOperationPorts ()

void	connectRF ()

void	findRF ()

void	findBusWidths ()

bool	findConnectedBusses (Connection &rs1, Connection &rs2, Connection &rd, Connection &simm, const bool &forwarding) const

std::unordered_map< std::string, InstructionBitVector * >	constructRInstructions (Port src1, Port src2) const

std::unordered_map< std::string, InstructionBitVector * >	constructIInstructions (Port src1, Port src2) const

std::unordered_map< std::string, InstructionBitVector * >	constructSInstructions (Port src1, Port src2) const

std::unordered_map< std::string, InstructionBitVector * >	constructBInstructions (Port src1, Port src2) const

std::unordered_map< std::string, InstructionBitVector * >	constructUJInstructions () const

void	addBitsToMap (std::unordered_map< std::string, InstructionBitVector * > instructions, const std::map< std::string, std::string > encodings, std::ofstream &stream) const

void	generateMap (const std::string &dstDirectory)

void	generateWrapper (HDLTemplateInstantiator &instantiator, const std::string &fileDst)

void	generateNOP ()

void	throwOperationNotFoundError (const std::string &op) const

void	throwTriggeringPortError (const BaseFUPort *port, const std::string &type) const

void	throwInputPortError (const BaseFUPort *port, const std::string &type) const

void	throwOutputPortError (const BaseFUPort *port, const std::string &type) const

void	throwOperandCountError (const std::string &op, int required, int found) const

Private Attributes
std::unordered_map< std::string, BaseFUPort * >	rs1Ports_

std::unordered_map< std::string, BaseFUPort * >	rs2Ports_

std::unordered_map< std::string, BaseFUPort * >	rdPorts_

std::unordered_map< std::string, BaseFUPort * >	simmPorts_

std::unordered_map< Port *, int >	sourcePortID_

std::unordered_map< Port *, std::vector< std::string > >	sourceOperationMap_

std::map< std::string, std::string >	rOperations_

std::map< std::string, std::string >	iOperations_

std::map< std::string, std::string >	sOperations_

std::map< std::string, std::string >	bOperations_

std::map< std::string, std::string >	ujOperations_

const Machine *	machine_

const BinaryEncoding *	bem_

std::vector< Bus * >	busses_

RegisterFile *	RF_

int	rs1BusWidth_

int	rs2BusWidth_

int	rdBusWidth_

int	simmBusWidth_

int	rs1BusStart_

int	rs2BusStart_

int	rdBusStart_

int	simmBusStart_

int	rs1RFStart_

int	rs2RFStart_

int	rdRFStart_

int	simmRFStart_

Bus *	rs1Bus_

Bus *	rs2Bus_

Bus *	rdBus_

Bus *	simmBus_

RFPort *	rs1RFPort_

RFPort *	rs2RFPort_

RFPort *	rdRFPort_

ProgramImageGenerator *	pig_

std::string	NOP_

bool	bypassInstructionRegister_

bool	hasForwarding_

bool	variableLengthOpLatency_

bool	eVariant_

Detailed Description

Definition at line 67 of file RV32MicroCodeGenerator.hh.

Constructor & Destructor Documentation

◆ RV32MicroCodeGenerator()

ProGe::RV32MicroCodeGenerator::RV32MicroCodeGenerator	(	const Machine &	machine,
		const BinaryEncoding &	bem
	)

Definition at line 80 of file RV32MicroCodeGenerator.cc.

     : machine_(&machine),
       bem_(&bem),
       RF_(NULL),
       rs1Bus_(NULL),
       rs2Bus_(NULL),
       rdBus_(NULL),
       rs1RFPort_(NULL),
       rs2RFPort_(NULL),
       rdRFPort_(NULL),
       pig_(new ProgramImageGenerator()),
       NOP_(""),
       bypassInstructionRegister_(false),
       hasForwarding_(false),
       variableLengthOpLatency_(false),
       eVariant_(false) {
     Machine::BusNavigator busNav = machine.busNavigator();
     for (int i = 0; i < busNav.count(); i++) {
         busses_.push_back(busNav.item(i));
     }
  
     initializeOperations();
  
     findOperationPorts();
     findOperationSources();
  
     pig_->loadBEM(bem);
     pig_->loadMachine(machine);
  
     generateNOP();
  
     findRF();
     connectRF();
     findBusWidths();
     if (RV32_RTL_GEN_VERBOSE) {
         if (hasForwarding_) {
             std::cout << "Generated bypass logic" << std::endl;
         } else {
             std::cout << "Not required connectivity for bypass logic"
                       << std::endl;
         }
     }
 }

References TTAMachine::Machine::busNavigator(), busses_, connectRF(), TTAMachine::Machine::Navigator< ComponentType >::count(), findBusWidths(), findOperationPorts(), findOperationSources(), findRF(), generateNOP(), hasForwarding_, initializeOperations(), TTAMachine::Machine::Navigator< ComponentType >::item(), ProgramImageGenerator::loadBEM(), ProgramImageGenerator::loadMachine(), machine, pig_, and RV32_RTL_GEN_VERBOSE.

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◆ ~RV32MicroCodeGenerator()

ProGe::RV32MicroCodeGenerator::~RV32MicroCodeGenerator ( )

Definition at line 125 of file RV32MicroCodeGenerator.cc.

125 { delete pig_; }

References pig_.

Member Function Documentation

◆ addBitsToMap()

void ProGe::RV32MicroCodeGenerator::addBitsToMap	(	std::unordered_map< std::string, InstructionBitVector * >	instructions,
		const std::map< std::string, std::string >	encodings,
		std::ofstream &	stream
	)		const

private

Definition at line 940 of file RV32MicroCodeGenerator.cc.

                                {
     assert(instructions.size() == encodings.size());
     for (const auto& op : instructions) {
         stream << "    elsif(fu_opcode(" << encodings.at(op.first).size()
                << " - 1 downto 0) = "
                << "\"" << encodings.at(op.first) << "\""
                << ") then" << std::endl
                << "      moves <= \"" << op.second->toString() << "\";"
                << std::endl;
         delete op.second;
     }
 }

References assert.

Referenced by generateMap().

◆ addBPorts()

void ProGe::RV32MicroCodeGenerator::addBPorts ( const std::string & opName )

private

Definition at line 369 of file RV32MicroCodeGenerator.cc.

                                                          {
     FunctionUnit* fu = mapFunctionUnit(opName);
     HWOperation* op = fu->operation(opName);
     if (op->operandCount() != 3) {
         throwOperandCountError(opName, 3, op->operandCount());
     }
     FUPort* simmPort = op->port(1);
     FUPort* rs1Port = op->port(2);
     FUPort* rs2Port = op->port(3);
     if (!simmPort->isTriggering()) {
         throwTriggeringPortError(simmPort, "imm");
     } else if (!rs1Port->isInput()) {
         throwInputPortError(rs1Port, "rs1");
     } else if (!rs2Port->isInput()) {
         throwInputPortError(rs1Port, "rs2");
     }
     rs1Ports_.insert({opName, rs1Port});
     simmPorts_.insert({opName, simmPort});
     rs2Ports_.insert({opName, rs2Port});
 }

References TTAMachine::Port::isInput(), TTAMachine::FUPort::isTriggering(), mapFunctionUnit(), TTAMachine::HWOperation::operandCount(), TTAMachine::FunctionUnit::operation(), TTAMachine::HWOperation::port(), rs1Ports_, rs2Ports_, simmPorts_, throwInputPortError(), throwOperandCountError(), and throwTriggeringPortError().

Referenced by findOperationPorts().

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◆ addIPorts()

void ProGe::RV32MicroCodeGenerator::addIPorts ( const std::string & opName )

private

Definition at line 340 of file RV32MicroCodeGenerator.cc.

                                                          {
     if (rOperations_.count(opName)) {
         return;
     }
     FunctionUnit* fu = mapFunctionUnit(opName);
     HWOperation* op = fu->operation(opName);
     const int operandCount = (opName == "calla") ? 2 : 3;
     if (op->operandCount() != operandCount) {
         throwOperandCountError(opName, operandCount, op->operandCount());
     }
     FUPort* rs1Port = op->port(1);
     FUPort* simmPort = op->port(2);
     BaseFUPort* rdPort;
     if (opName != "calla") {
         rdPort = op->port(3);
         if (!rdPort->isOutput()) {
             throwOutputPortError(rdPort, "rd");
         }
     } else {
         rs1Port = op->port(2);
         simmPort = op->port(1);
         rdPort = machine_->controlUnit()->returnAddressPort();
     }
     rs1Ports_.insert({opName, rs1Port});
     simmPorts_.insert({opName, simmPort});
     rdPorts_.insert({opName, rdPort});
 }

References TTAMachine::Machine::controlUnit(), TTAMachine::Port::isOutput(), machine_, mapFunctionUnit(), TTAMachine::HWOperation::operandCount(), TTAMachine::FunctionUnit::operation(), TTAMachine::HWOperation::port(), rdPorts_, TTAMachine::ControlUnit::returnAddressPort(), rOperations_, rs1Ports_, simmPorts_, throwOperandCountError(), and throwOutputPortError().

Referenced by findOperationPorts().

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◆ addRPorts()

void ProGe::RV32MicroCodeGenerator::addRPorts ( const std::string & opName )

private

Definition at line 306 of file RV32MicroCodeGenerator.cc.

                                                          {
     FunctionUnit* fu = mapFunctionUnit(opName);
     HWOperation* op = fu->operation(opName);
     if (op->operandCount() != 3) {
         throwOperandCountError(opName, 3, op->operandCount());
     }
     FUPort* rs1Port = op->port(1);
     ;
     FUPort* rs2Port = op->port(2);
     FUPort* rdPort = op->port(3);
     if (!rs1Port->isTriggering()) {
         throwTriggeringPortError(rs1Port, "rs1");
     }
     if (!rs2Port->isInput()) {
         throwInputPortError(rs2Port, "rs2");
     }
     if (!rdPort->isOutput()) {
         throwOutputPortError(rdPort, "rd");
     }
     rs1Ports_.insert({opName, rs1Port});
     rs2Ports_.insert({opName, rs2Port});
     // Do not add custom ops to simm ports
     if (MapTools::containsValue(operationNameTable, opName)) {
         const std::string riscvOpName =MapTools::keyForValue
         <string, map<string, string>, string>(operationNameTable, opName);
         // Do not add M-extension ops
         if (!VectorTools::containsValue(mExtensionOps, riscvOpName)) {
             simmPorts_.insert({opName, rs2Port});
         }
     }
     rdPorts_.insert({opName, rdPort});
 }

References VectorTools::containsValue(), MapTools::containsValue(), TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), TTAMachine::FUPort::isTriggering(), MapTools::keyForValue(), mapFunctionUnit(), mExtensionOps, TTAMachine::HWOperation::operandCount(), TTAMachine::FunctionUnit::operation(), operationNameTable, TTAMachine::HWOperation::port(), rdPorts_, rs1Ports_, rs2Ports_, simmPorts_, throwInputPortError(), throwOperandCountError(), throwOutputPortError(), and throwTriggeringPortError().

Referenced by findOperationPorts().

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◆ addRs1ForwardingConditions()

void ProGe::RV32MicroCodeGenerator::addRs1ForwardingConditions	(	std::map< std::string, std::string >	ops,
		std::unordered_map< std::string, InstructionBitVector * >(ProGe::RV32MicroCodeGenerator::)(Port p1, Port *p2) const	instructionFunc,
		std::ofstream &	stream
	)		const

private

Definition at line 1028 of file RV32MicroCodeGenerator.cc.

                                {
     bool firstOpcodeCond = true;
     for (const auto& op : ops) {
         std::string opcodeCond = "        elsif ";
         if (firstOpcodeCond) {
             opcodeCond = "        if ";
             firstOpcodeCond = false;
         }
         stream << opcodeCond << "fu_opcode(" << op.second.size()
                << "-1 downto 0) = \"" << op.second << "\"";
         if (rOperations_.count(op.first) && iOperations_.count(op.first)) {
             stream << " or fu_opcode(" << iOperations_.at(op.first).size()
                    << "-1 downto 0) = \"" << iOperations_.at(op.first)
                    << "\"";
         }
         stream << "then\n";
         bool firstTargetCond = true;
         for (const auto& p : sourceOperationMap_) {
             std::string targetCond = "          elsif ";
             if (firstTargetCond) {
                 targetCond = "          if ";
                 firstTargetCond = false;
             }
             stream << targetCond + "target_fu_r = "
                    << sourcePortID_.at(p.first) << " then \n";
             std::unordered_map<std::string, InstructionBitVector*>
                 instructions = (this->*instructionFunc)(p.first, rs2RFPort_);
             std::string bits = instructions.at(op.first)->toString();
             reverse(bits.begin(), bits.end());
             bits = bits.substr(rs1BusStart_, rs1BusWidth_);
             reverse(bits.begin(), bits.end());
             stream << "            moves(rs1_start_c + rs1_width_c -1 downto"
                    << " rs1_start_c)"
                    << " <= \"" << bits << "\";\n";
             for (const auto& val : instructions) {
                 delete val.second;
             }
         }
         stream << "          end if;" << std::endl;
     }
     stream << "        end if;" << std::endl;
 }

References iOperations_, rOperations_, rs1BusStart_, rs1BusWidth_, rs2RFPort_, sourceOperationMap_, and sourcePortID_.

Referenced by generateMap().

◆ addRs2ForwardingConditions()

void ProGe::RV32MicroCodeGenerator::addRs2ForwardingConditions	(	std::map< std::string, std::string >	ops,
		std::unordered_map< std::string, InstructionBitVector * >(ProGe::RV32MicroCodeGenerator::)(Port p1, Port *p2) const	instructionFunc,
		std::ofstream &	stream
	)		const

private

Definition at line 1077 of file RV32MicroCodeGenerator.cc.

                                {
     bool firstOpcodeCond = true;
     for (const auto& op : ops) {
         std::string opcodeCond = "        elsif ";
         if (firstOpcodeCond) {
             opcodeCond = "        if ";
             firstOpcodeCond = false;
         }
         stream << opcodeCond << "fu_opcode(" << op.second.size()
                << "-1 downto 0) = \"" << op.second << "\" then\n";
         bool firstTargetCond = true;
         for (const auto& p : sourceOperationMap_) {
             std::string targetCond = "          elsif ";
             if (firstTargetCond) {
                 targetCond = "          if ";
                 firstTargetCond = false;
             }
             stream << targetCond + "target_fu_r = "
                    << sourcePortID_.at(p.first) << " then \n";
             std::unordered_map<std::string, InstructionBitVector*>
                 instructions = (this->*instructionFunc)(rs1RFPort_, p.first);
             std::string bits = instructions.at(op.first)->toString();
             reverse(bits.begin(), bits.end());
             bits = bits.substr(rs2BusStart_, rs2BusWidth_);
             reverse(bits.begin(), bits.end());
             stream << "            moves(rs2_start_c + rs2_width_c -1 downto"
                    << " rs2_start_c)"
                    << " <= \"" << bits << "\";\n";
             for (const auto& val : instructions) {
                 delete val.second;
             }
         }
         stream << "          end if;" << std::endl;
     }
     stream << "        end if;" << std::endl;
 }

References rs1RFPort_, rs2BusStart_, rs2BusWidth_, sourceOperationMap_, and sourcePortID_.

Referenced by generateMap().

◆ addSPorts()

void ProGe::RV32MicroCodeGenerator::addSPorts ( const std::string & opName )

private

Definition at line 415 of file RV32MicroCodeGenerator.cc.

                                                          {
     FunctionUnit* fu = mapFunctionUnit(opName);
     HWOperation* op = fu->operation(opName);
     if (op->operandCount() != 3) {
         throwOperandCountError(opName, 3, op->operandCount());
     }
     FUPort* rs1Port = op->port(1);
     FUPort* simmPort = op->port(2);
     FUPort* rs2Port = op->port(3);
     if (!rs1Port->isTriggering()) {
         throwTriggeringPortError(rs1Port, "rs1");
     }
     if (!rs2Port->isInput()) {
         throwInputPortError(rs2Port, "rs2");
     }
     if (!simmPort->isInput()) {
         throwInputPortError(simmPort, "imm");
     }
     rs1Ports_.insert({opName, rs1Port});
     simmPorts_.insert({opName, simmPort});
     rs2Ports_.insert({opName, rs2Port});
 }

References TTAMachine::Port::isInput(), TTAMachine::FUPort::isTriggering(), mapFunctionUnit(), TTAMachine::HWOperation::operandCount(), TTAMachine::FunctionUnit::operation(), TTAMachine::HWOperation::port(), rs1Ports_, rs2Ports_, simmPorts_, throwInputPortError(), throwOperandCountError(), and throwTriggeringPortError().

Referenced by findOperationPorts().

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◆ addUJPorts()

void ProGe::RV32MicroCodeGenerator::addUJPorts ( const std::string & opName )

private

Definition at line 391 of file RV32MicroCodeGenerator.cc.

                                                           {
     if (opName == "move") {
         return;
     }
     ControlUnit* fu = dynamic_cast<ControlUnit*>(mapFunctionUnit(opName));
     HWOperation* op = fu->operation(opName);
     FUPort* simmPort = op->port(1);
     BaseFUPort* rdPort;
     if (opName == "apc") {
         rdPort = op->port(2);
         if (!rdPort->isOutput()) {
             throwOutputPortError(rdPort, "rd");
         }
     } else {
         rdPort = fu->returnAddressPort();
     }
     if (!simmPort->isTriggering()) {
         throwTriggeringPortError(simmPort, "imm");
     }
     rdPorts_.insert({opName, rdPort});
     simmPorts_.insert({opName, simmPort});
 }

References TTAMachine::Port::isOutput(), TTAMachine::FUPort::isTriggering(), mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), TTAMachine::HWOperation::port(), rdPorts_, TTAMachine::ControlUnit::returnAddressPort(), simmPorts_, throwOutputPortError(), and throwTriggeringPortError().

Referenced by findOperationPorts().

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◆ connectRF()

void ProGe::RV32MicroCodeGenerator::connectRF ( )

private

Definition at line 520 of file RV32MicroCodeGenerator.cc.

                                   {
     RFPort* rs1RFPort = NULL;
     RFPort* rs2RFPort = NULL;
     RFPort* rdRFPort = NULL;
  
     std::vector<RFPort*> RFOutputPorts;
     std::vector<RFPort*> RFInputPorts;
     for (int i = 0; i < RF_->portCount(); i++) {
         RFPort* tmpPort = RF_->port(i);
         if (tmpPort->outputSocket() != NULL) {
             RFOutputPorts.push_back(tmpPort);
         } else if (tmpPort->inputSocket() != NULL) {
             RFInputPorts.push_back(tmpPort);
         }
     }
  
     assert(RFInputPorts.size() > 0);
     assert(RFOutputPorts.size() > 1);
  
     Connection rs1;
     Connection rs2;
     Connection rd;
     Connection simm;
  
     // Find candidates for rs1, rs2 and rd busses.
     bool success = false;
     bool forwarding = false;
     for (int l = 0; l < 2 && !success; l++) {
         // First try with forwarding enabled
         forwarding = !forwarding;
         for (unsigned int i = 0; i < RFOutputPorts.size() && !success; i++) {
             std::vector<RFPort*> tmpRFOutputPorts = RFOutputPorts;
             rs1RFPort = RFOutputPorts.at(i);
             tmpRFOutputPorts.erase(tmpRFOutputPorts.begin() + i);
             for (unsigned int j = 0; j < tmpRFOutputPorts.size() && !success;
                  j++) {
                 rs2RFPort = tmpRFOutputPorts.at(j);
                 for (unsigned int k = 0; k < RFInputPorts.size() && !success;
                      k++) {
                     std::vector<RFPort*> tmpRFInputPorts;
                     tmpRFInputPorts = RFInputPorts;
                     rdRFPort = RFInputPorts.at(k);
  
                     rs1.port = rs1RFPort;
                     rs2.port = rs2RFPort;
                     rd.port = rdRFPort;
  
                     rs1.bus = NULL;
                     rs2.bus = NULL;
                     rd.bus = NULL;
                     simm.bus = NULL;
  
                     success =
                         findConnectedBusses(rs1, rs2, rd, simm, forwarding);
                     if (success) {
                         break;
                     }
                 }
             }
         }
     }
  
     if (!success) {
         std::string msg =
             "Could not find enough connectivity in the "
             "interconnect to construct RISC-V control and decode logic. Make "
             "sure "
             "the minimum connections are in place and that the operand-port "
             "bindings are valid in FUs";
         throw InvalidData(__FILE__, __LINE__, __func__, msg);
     }
     hasForwarding_ = forwarding;
  
     rs1Bus_ = rs1.bus;
     rs2Bus_ = rs2.bus;
     rdBus_ = rd.bus;
     simmBus_ = simm.bus;
     rs1RFPort_ = rs1RFPort;
     rs2RFPort_ = rs2RFPort;
     rdRFPort_ = rdRFPort;
 }

References __func__, assert, ProGe::MicroCodeGenerator::Connection::bus, findConnectedBusses(), hasForwarding_, TTAMachine::Port::inputSocket(), TTAMachine::Port::outputSocket(), ProGe::MicroCodeGenerator::Connection::port, TTAMachine::BaseRegisterFile::port(), TTAMachine::Unit::portCount(), rdBus_, rdRFPort_, RF_, rs1Bus_, rs1RFPort_, rs2Bus_, rs2RFPort_, and simmBus_.

Referenced by RV32MicroCodeGenerator().

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◆ constructBInstructions()

std::unordered_map< std::string, InstructionBitVector * > ProGe::RV32MicroCodeGenerator::constructBInstructions	(	Port *	src1,
		Port *	src2
	)		const

private

Definition at line 831 of file RV32MicroCodeGenerator.cc.

                                                                            {
     std::unordered_map<std::string, InstructionBitVector*> retval;
     CodeCompressorPlugin* compressor = &pig_->compressor();
     for (const auto& op : bOperations_) {
         Instruction* instruction = new Instruction();
         HWOperation* operation =
             mapFunctionUnit(op.first)->operation(op.first);
  
         FUPort* rs1Port = static_cast<FUPort*>(rs1Ports_.at(op.first));
         FUPort* simmPort = static_cast<FUPort*>(simmPorts_.at(op.first));
         FUPort* rs2Port = static_cast<FUPort*>(rs2Ports_.at(op.first));
  
         instruction->addMove(std::make_shared<Move>(
             new TerminalImmediate(SimValue(0, simmBus_->width())),
             new TerminalFUPort(*simmPort, *operation), *simmBus_));
  
         if (dynamic_cast<RFPort*>(src1)) {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*src1, 0), new TerminalFUPort(*rs1Port),
                 *rs1Bus_));
         } else {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*static_cast<BaseFUPort*>(src1)),
                 new TerminalFUPort(*rs1Port), *rs1Bus_));
         }
  
         if (dynamic_cast<RFPort*>(src2)) {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*src2, 0), new TerminalFUPort(*rs2Port),
                 *rs2Bus_));
         } else {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*static_cast<BaseFUPort*>(src2)),
                 new TerminalFUPort(*rs2Port), *rs2Bus_));
         }
  
         InstructionBitVector* bits =
             compressor->bemInstructionBits(*instruction);
         delete instruction;
         retval.insert({op.first, bits});
     }
     return retval;
 }

References TTAProgram::Instruction::addMove(), CodeCompressorPlugin::bemInstructionBits(), bOperations_, ProgramImageGenerator::compressor(), mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), pig_, rs1Bus_, rs1Ports_, rs2Bus_, rs2Ports_, simmBus_, simmPorts_, and TTAMachine::Bus::width().

Referenced by generateMap().

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◆ constructIInstructions()

std::unordered_map< std::string, InstructionBitVector * > ProGe::RV32MicroCodeGenerator::constructIInstructions	(	Port *	src1,
		Port *	src2
	)		const

private

Definition at line 723 of file RV32MicroCodeGenerator.cc.

                                {
     std::unordered_map<std::string, InstructionBitVector*> retval;
     CodeCompressorPlugin* compressor = &pig_->compressor();
     for (const auto& op : iOperations_) {
         Instruction* instruction = new Instruction();
  
         HWOperation* operation =
             mapFunctionUnit(op.first)->operation(op.first);
  
         FUPort* rdPort = static_cast<FUPort*>(rdPorts_.at(op.first));
  
         // ALU operations are a special case as they are shared with R type
         if (op.first != "calla") {
             FUPort* simmPort = static_cast<FUPort*>(simmPorts_.at(op.first));
             FUPort* rs1Port = static_cast<FUPort*>(rs1Ports_.at(op.first));
  
             if (dynamic_cast<RFPort*>(src1)) {
                 instruction->addMove(std::make_shared<Move>(
                     new TerminalRegister(*src1, 0),
                     new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
             } else {
                 instruction->addMove(std::make_shared<Move>(
                     new TerminalFUPort(*static_cast<BaseFUPort*>(src1)),
                     new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
             }
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalImmediate(SimValue(0, simmBus_->width())),
                 new TerminalFUPort(*simmPort), *simmBus_));
  
         } else {
             FUPort* rs1Port = static_cast<FUPort*>(rs1Ports_.at(op.first));
             FUPort* simmPort = static_cast<FUPort*>(simmPorts_.at(op.first));
  
             if (dynamic_cast<RFPort*>(src1)) {
                 instruction->addMove(std::make_shared<Move>(
                     new TerminalRegister(*src1, 0),
                     new TerminalFUPort(*rs1Port), *rs1Bus_));
             } else {
                 instruction->addMove(std::make_shared<Move>(
                     new TerminalFUPort(*static_cast<BaseFUPort*>(src1)),
                     new TerminalFUPort(*rs1Port), *rs1Bus_));
             }
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalImmediate(SimValue(0, simmBus_->width())),
                 new TerminalFUPort(*simmPort, *operation), *simmBus_));
         }
  
         instruction->addMove(std::make_shared<Move>(
             new TerminalFUPort(*rdPort), new TerminalRegister(*rdRFPort_, 0),
             *rdBus_));
  
         InstructionBitVector* bits =
             compressor->bemInstructionBits(*instruction);
         delete instruction;
         retval.insert({op.first, bits});
     }
     return retval;
 }

References TTAProgram::Instruction::addMove(), CodeCompressorPlugin::bemInstructionBits(), ProgramImageGenerator::compressor(), iOperations_, mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), pig_, rdBus_, rdPorts_, rdRFPort_, rs1Bus_, rs1Ports_, simmBus_, simmPorts_, and TTAMachine::Bus::width().

Referenced by generateMap().

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◆ constructRInstructions()

std::unordered_map< std::string, InstructionBitVector * > ProGe::RV32MicroCodeGenerator::constructRInstructions	(	Port *	src1,
		Port *	src2
	)		const

private

Definition at line 678 of file RV32MicroCodeGenerator.cc.

                                                                            {
     std::unordered_map<std::string, InstructionBitVector*> retval;
     CodeCompressorPlugin* compressor = &pig_->compressor();
     for (const auto& op : rOperations_) {
         Instruction* instruction = new Instruction();
         HWOperation* operation =
             mapFunctionUnit(op.first)->operation(op.first);
  
         FUPort* rs1Port = static_cast<FUPort*>(rs1Ports_.at(op.first));
         FUPort* rs2Port = static_cast<FUPort*>(rs2Ports_.at(op.first));
         FUPort* rdPort = static_cast<FUPort*>(rdPorts_.at(op.first));
  
         if (dynamic_cast<RFPort*>(src1)) {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*src1, 0),
                 new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
         } else {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*static_cast<BaseFUPort*>(src1)),
                 new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
         }
  
         if (dynamic_cast<RFPort*>(src2)) {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*src2, 0), new TerminalFUPort(*rs2Port),
                 *rs2Bus_));
         } else {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*static_cast<BaseFUPort*>(src2)),
                 new TerminalFUPort(*rs2Port), *rs2Bus_));
         }
  
         instruction->addMove(std::make_shared<Move>(
             new TerminalFUPort(*rdPort), new TerminalRegister(*rdRFPort_, 0),
             *rdBus_));
  
         InstructionBitVector* bits =
             compressor->bemInstructionBits(*instruction);
         delete instruction;
         retval.insert({op.first, bits});
     }
     return retval;
 }

References TTAProgram::Instruction::addMove(), CodeCompressorPlugin::bemInstructionBits(), ProgramImageGenerator::compressor(), mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), pig_, rdBus_, rdPorts_, rdRFPort_, rOperations_, rs1Bus_, rs1Ports_, rs2Bus_, and rs2Ports_.

Referenced by generateMap().

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◆ constructSInstructions()

std::unordered_map< std::string, InstructionBitVector * > ProGe::RV32MicroCodeGenerator::constructSInstructions	(	Port *	src1,
		Port *	src2
	)		const

private

Definition at line 786 of file RV32MicroCodeGenerator.cc.

                                                                            {
     std::unordered_map<std::string, InstructionBitVector*> retval;
     CodeCompressorPlugin* compressor = &pig_->compressor();
     for (const auto& op : sOperations_) {
         Instruction* instruction = new Instruction();
         HWOperation* operation =
             mapFunctionUnit(op.first)->operation(op.first);
  
         FUPort* simmPort = static_cast<FUPort*>(simmPorts_.at(op.first));
         FUPort* rs1Port = static_cast<FUPort*>(rs1Ports_.at(op.first));
         FUPort* rs2Port = static_cast<FUPort*>(rs2Ports_.at(op.first));
  
         if (dynamic_cast<RFPort*>(src1)) {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*src1, 0),
                 new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
         } else {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*static_cast<BaseFUPort*>(src1)),
                 new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
         }
  
         instruction->addMove(std::make_shared<Move>(
             new TerminalImmediate(SimValue(0, simmBus_->width())),
             new TerminalFUPort(*simmPort), *simmBus_));
  
         if (dynamic_cast<RFPort*>(src2)) {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*src2, 0), new TerminalFUPort(*rs2Port),
                 *rs2Bus_));
         } else {
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*static_cast<BaseFUPort*>(src2)),
                 new TerminalFUPort(*rs2Port), *rs2Bus_));
         }
  
         InstructionBitVector* bits =
             compressor->bemInstructionBits(*instruction);
         delete instruction;
         retval.insert({op.first, bits});
     }
     return retval;
 }

References TTAProgram::Instruction::addMove(), CodeCompressorPlugin::bemInstructionBits(), ProgramImageGenerator::compressor(), mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), pig_, rs1Bus_, rs1Ports_, rs2Bus_, rs2Ports_, simmBus_, simmPorts_, sOperations_, and TTAMachine::Bus::width().

Referenced by generateMap().

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◆ constructUJInstructions()

std::unordered_map< std::string, InstructionBitVector * > ProGe::RV32MicroCodeGenerator::constructUJInstructions ( ) const

private

Definition at line 876 of file RV32MicroCodeGenerator.cc.

                                                       {
     std::unordered_map<std::string, InstructionBitVector*> retval;
     CodeCompressorPlugin* compressor = &pig_->compressor();
     InstructionBitVector* bits;
  
     for (const auto& op : ujOperations_) {
         Instruction* instruction = new Instruction();
         if (op.first == "move") {
             HWOperation* operation = mapFunctionUnit("add")->operation("add");
             FUPort* rs1Port = static_cast<FUPort*>(rs1Ports_.at("add"));
             FUPort* simmPort = static_cast<FUPort*>(simmPorts_.at("add"));
             FUPort* rdPort = static_cast<FUPort*>(rdPorts_.at("add"));
             instruction->addMove(std::make_shared<Move>(
                 new TerminalRegister(*rs1RFPort_, 0),
                 new TerminalFUPort(*rs1Port, *operation), *rs1Bus_));
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalImmediate(SimValue(0, simmBus_->width())),
                 new TerminalFUPort(*simmPort), *simmBus_));
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*rdPort),
                 new TerminalRegister(*rdRFPort_, 0), *rdBus_));
  
             bits = compressor->bemInstructionBits(*instruction);
             retval.insert({"move", bits});
             delete instruction;
         } else if (op.first == "callr" or op.first == "apc") {
             FUPort* rdPort = static_cast<FUPort*>(rdPorts_.at(op.first));
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*rdPort),
                 new TerminalRegister(*rdRFPort_, 0), *rdBus_));
  
             bits = compressor->bemInstructionBits(*instruction);
             delete instruction;
             retval.insert({op.first, bits});
  
         } else {
             FUPort* simmPort = static_cast<FUPort*>(simmPorts_.at(op.first));
             FUPort* rdPort = static_cast<FUPort*>(rdPorts_.at(op.first));
  
             HWOperation* operation =
                 mapFunctionUnit(op.first)->operation(op.first);
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalImmediate(SimValue(0, simmBus_->width())),
                 new TerminalFUPort(*simmPort, *operation), *simmBus_));
  
             instruction->addMove(std::make_shared<Move>(
                 new TerminalFUPort(*rdPort),
                 new TerminalRegister(*rdRFPort_, 0), *rdBus_));
  
             bits = compressor->bemInstructionBits(*instruction);
             delete instruction;
  
             retval.insert({op.first, bits});
         }
     }
  
     return retval;
 }

References TTAProgram::Instruction::addMove(), CodeCompressorPlugin::bemInstructionBits(), ProgramImageGenerator::compressor(), mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), pig_, rdBus_, rdPorts_, rdRFPort_, rs1Bus_, rs1Ports_, rs1RFPort_, simmBus_, simmPorts_, ujOperations_, and TTAMachine::Bus::width().

Referenced by generateMap().

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◆ findBusWidths()

void ProGe::RV32MicroCodeGenerator::findBusWidths ( )

private

Definition at line 490 of file RV32MicroCodeGenerator.cc.

                                       {
     for (int i = 0; i < bem_->moveSlotCount(); i++) {
         MoveSlot& slot = bem_->moveSlot(i);
         if (slot.name() == rs1Bus_->name()) {
             rs1BusWidth_ = slot.width();
             assert(slot.hasDestinationField());
             rs1RFStart_ = slot.destinationField().width();
             rs1BusStart_ = slot.bitPosition();
         } else if (slot.name() == rs2Bus_->name()) {
             rs2BusWidth_ = slot.width();
             assert(slot.hasDestinationField());
             rs2RFStart_ = slot.destinationField().width();
             rs2BusStart_ = slot.bitPosition();
         } else if (slot.name() == rdBus_->name()) {
             rdBusWidth_ = slot.width();
             rdRFStart_ = 0;
             rdBusStart_ = slot.bitPosition();
         } else if (slot.name() == simmBus_->name()) {
             simmBusWidth_ = slot.width();
             simmRFStart_ = 0;
             simmBusStart_ = slot.bitPosition();
         }
     }
     assert(rs1BusWidth_ > 0);
     assert(rs2BusWidth_ > 0);
     assert(rdBusWidth_ > 0);
     assert(simmBusWidth_ > 0);
 }

References assert, bem_, InstructionField::bitPosition(), MoveSlot::destinationField(), MoveSlot::hasDestinationField(), BinaryEncoding::moveSlot(), BinaryEncoding::moveSlotCount(), MoveSlot::name(), TTAMachine::Component::name(), rdBus_, rdBusStart_, rdBusWidth_, rdRFStart_, rs1Bus_, rs1BusStart_, rs1BusWidth_, rs1RFStart_, rs2Bus_, rs2BusStart_, rs2BusWidth_, rs2RFStart_, simmBus_, simmBusStart_, simmBusWidth_, simmRFStart_, SlotField::width(), and MoveSlot::width().

Referenced by RV32MicroCodeGenerator().

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◆ findConnectedBusses()

bool ProGe::RV32MicroCodeGenerator::findConnectedBusses	(	Connection &	rs1,
		Connection &	rs2,
		Connection &	rd,
		Connection &	simm,
		const bool &	forwarding
	)		const

private

Definition at line 613 of file RV32MicroCodeGenerator.cc.

                                   {
     std::set<Port*> rs1Ports = operationPorts(rs1Ports_);
     rs1Ports.insert(rs1.port);
  
     std::set<Port*> rs2Ports = operationPorts(rs2Ports_);
     rs2Ports.insert(rs2.port);
  
     std::set<Port*> simmPorts = operationPorts(simmPorts_);
  
     std::set<Port*> rdPorts = operationPorts(rdPorts_);
  
     if (forwarding) {
         rs1Ports.insert(rdPorts.begin(), rdPorts.end());
         rs2Ports.insert(rdPorts.begin(), rdPorts.end());
     }
  
     rdPorts.insert(rd.port);
  
     // Brute forces all combinations until all ports can be mapped to a bus
     for (unsigned int i = 0; i < busses_.size(); i++) {
         std::vector<Bus*> tmpBusses = busses_;
         rs1.bus = NULL;
         rs2.bus = NULL;
         rd.bus = NULL;
         simm.bus = NULL;
         Bus* tmpBus = busses_.at(i);
         if (!MachineConnectivityCheck::isConnected(rs1Ports, *tmpBus)) {
             continue;
         }
         rs1.bus = tmpBus;
         tmpBusses.erase(tmpBusses.begin() + i);
         rs2.bus = NULL;
         for (unsigned int j = 0; j < tmpBusses.size(); j++) {
             tmpBus = tmpBusses.at(j);
             if (!MachineConnectivityCheck::isConnected(rs2Ports, *tmpBus)) {
                 continue;
             }
             rs2.bus = tmpBus;
             tmpBusses.erase(tmpBusses.begin() + j);
             for (unsigned int k = 0; k < tmpBusses.size(); k++) {
                 tmpBus = tmpBusses.at(k);
                 if (!MachineConnectivityCheck::isConnected(
                         rdPorts, *tmpBus)) {
                     continue;
                 }
                 rd.bus = tmpBus;
                 tmpBusses.erase(tmpBusses.begin() + k);
                 for (unsigned int h = 0; h < tmpBusses.size(); h++) {
                     tmpBus = tmpBusses.at(h);
                     if (MachineConnectivityCheck::isConnected(
                             simmPorts, *tmpBus) &&
                         tmpBus->immediateWidth() > 0) {
                         simm.bus = tmpBus;
                         return true;
                     }
                 }
             }
         }
     }
     return false;
 }

References ProGe::MicroCodeGenerator::Connection::bus, busses_, TTAMachine::Bus::immediateWidth(), MachineConnectivityCheck::isConnected(), operationPorts(), ProGe::MicroCodeGenerator::Connection::port, rdPorts_, rs1Ports_, rs2Ports_, and simmPorts_.

Referenced by connectRF().

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◆ findOperationPorts()

void ProGe::RV32MicroCodeGenerator::findOperationPorts ( )

private

Definition at line 439 of file RV32MicroCodeGenerator.cc.

                                            {
     for (const auto& op : rOperations_) {
         addRPorts(op.first);
     }
     for (const auto& op : iOperations_) {
         addIPorts(op.first);
     }
     for (const auto& op : sOperations_) {
         addSPorts(op.first);
     }
     for (const auto& op : bOperations_) {
         addBPorts(op.first);
     }
     for (const auto& op : ujOperations_) {
         addUJPorts(op.first);
     }
 }

References addBPorts(), addIPorts(), addRPorts(), addSPorts(), addUJPorts(), bOperations_, iOperations_, rOperations_, sOperations_, and ujOperations_.

Referenced by RV32MicroCodeGenerator().

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◆ findOperationSources()

void ProGe::RV32MicroCodeGenerator::findOperationSources ( )

private

Definition at line 128 of file RV32MicroCodeGenerator.cc.

                                              {
     for (const auto& op : rdPorts_) {
         if (sourceOperationMap_.count(op.second)) {
             sourceOperationMap_.at(op.second).push_back(op.first);
         } else {
             sourceOperationMap_.insert({op.second, {op.first}});
         }
     }
 }

References rdPorts_, and sourceOperationMap_.

Referenced by RV32MicroCodeGenerator().

◆ findRF()

void ProGe::RV32MicroCodeGenerator::findRF ( )

private

Definition at line 467 of file RV32MicroCodeGenerator.cc.

                                {
     Machine::RegisterFileNavigator rfNav = machine_->registerFileNavigator();
     // TODO: Design can have multiple register files. Iterate over all of
     // them and find one that fits based on connectivity.
     for (int i = 0; i < rfNav.count(); i++) {
         RegisterFile* rf = rfNav.item(0);
         if (rf->inputPortCount() > 0 && rf->outputPortCount() > 1 &&
             rf->zeroRegister()) {
             if (rf->size() > 31 && rf->width() == 32) {
                 RF_ = rf;
             } else if (rf->size() == 16 && rf->width() == 32) {
                 RF_ = rf;
                 eVariant_ = true;
             }
         }
     }
     if (RF_ == NULL) {
         std::string msg = "Could not find a valid register file for RISC-V";
         throw InvalidData(__FILE__, __LINE__, __func__, msg);
     }
 }

References __func__, TTAMachine::Machine::Navigator< ComponentType >::count(), eVariant_, TTAMachine::Unit::inputPortCount(), TTAMachine::Machine::Navigator< ComponentType >::item(), machine_, TTAMachine::Unit::outputPortCount(), TTAMachine::Machine::registerFileNavigator(), RF_, TTAMachine::BaseRegisterFile::size(), TTAMachine::BaseRegisterFile::width(), and TTAMachine::RegisterFile::zeroRegister().

Referenced by RV32MicroCodeGenerator().

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◆ generateFUTargetProcess()

void ProGe::RV32MicroCodeGenerator::generateFUTargetProcess ( std::ofstream & stream )

private

Definition at line 957 of file RV32MicroCodeGenerator.cc.

                                                                    {
     std::unordered_map<std::string, std::string> operations;
     operations.insert(rOperations_.begin(), rOperations_.end());
     operations.insert(iOperations_.begin(), iOperations_.end());
     operations.insert(sOperations_.begin(), sOperations_.end());
     operations.insert(bOperations_.begin(), bOperations_.end());
     operations.insert(ujOperations_.begin(), ujOperations_.end());
     int len = std::ceil(std::log2(sourceOperationMap_.size()));
  
     stream << "  process(fu_opcode)" << std::endl
            << "  begin" << std::endl
            << "    target_fu <= to_unsigned(0, " << len << ");" << std::endl;
  
     int id = 0;
     bool firstCond = true;
     std::string cond;
     for (const auto& p : sourceOperationMap_) {
         sourcePortID_.insert({p.first, id});
         for (const auto& op : p.second) {
             if (firstCond) {
                 cond = "    if ";
                 firstCond = false;
             } else {
                 cond = "    elsif ";
             }
             // Add is a special case as it is used in LUI
             if (op == "add") {
                 int iLen = iOperations_.at(op).size();
                 int uLen = ujOperations_.at("move").size();
                 stream << cond << "fu_opcode(" << iLen << "-1 downto 0)"
                        << " = \"" << iOperations_.at(op) << "\""
                        << " or "
                        << "fu_opcode = \"" << rOperations_.at(op)
                        << "\" or fu_opcode(" << uLen << "-1 downto 0) = \""
                        << ujOperations_.at("move") << "\""
                        << " then\n";
  
             } else if (iOperations_.count(op) && rOperations_.count(op)) {
                 int iLen = iOperations_.at(op).size();
                 stream << cond << "fu_opcode(" << iLen << "-1 downto 0)"
                        << " = \"" << iOperations_.at(op) << "\"  or "
                        << "fu_opcode = \"" << rOperations_.at(op)
                        << "\" then\n";
             } else {
                 int opLen = operations.at(op).size();
                 stream << cond << "fu_opcode(" << opLen << "-1 downto 0)"
                        << "= \"" << operations.at(op) << "\" then\n";
             }
             stream << "      target_fu <= to_unsigned(" << id << ", " << len
                    << ");\n";
         }
         id++;
     }
     stream << "    end if;" << std::endl << "  end process;" << std::endl;
  
     stream << std::endl << std::endl;
     stream << "  process(clk, rstx)" << std::endl
            << "  begin" << std::endl
            << "    if(rstx = '0') then" << std::endl
            << "      target_fu_r <= (others => '0');" << std::endl
            << "    elsif clk'event and clk = '1' then" << std::endl
            << "      if glock_in = '0' and halt = '0' then" << std::endl
            << "        target_fu_r <= target_fu;" << std::endl
            << "      end if;" << std::endl
            << "    end if;" << std::endl
            << "  end process;" << std::endl
            << std::endl
            << std::endl;
 }

References bOperations_, iOperations_, rOperations_, sOperations_, sourceOperationMap_, sourcePortID_, and ujOperations_.

Referenced by generateMap().

◆ generateMap()

void ProGe::RV32MicroCodeGenerator::generateMap ( const std::string & dstDirectory )

private

Definition at line 1120 of file RV32MicroCodeGenerator.cc.

                                                                  {
     /*TODO: The if structure should be replaced with a case statement
             The problem is that the fu_opcode's width is different between
             formats. Don't care states in a case statement
              is a VHDL-2OO8 feature
     */
     const std::string DS = FileSystem::DIRECTORY_SEPARATOR;
     std::string mapFile = dstDirectory + DS + "rv32_microcode.vhdl";
  
     std::ofstream stream;
     stream.open(mapFile);
  
     stream << "library IEEE;" << std::endl
            << "use IEEE.std_logic_1164.all;" << std::endl
            << "use IEEE.numeric_std.all;" << std::endl
            << "use work.tta0_globals.all;" << std::endl
            << std::endl
            << std::endl;
  
     stream << "entity rv32_microcode is" << std::endl << "port(" << std::endl;
     if (hasForwarding_) {
         stream << "  clk            : in std_logic;" << std::endl
                << "  rstx           : in std_logic;" << std::endl
                << "  glock_in       : in std_logic;" << std::endl
                << "  data_hazard_in : in std_logic;" << std::endl
                << "  rs1_hazard_in  : in std_logic;" << std::endl
                << "  rs2_hazard_in  : in std_logic;" << std::endl
                << "  halt           : in std_logic;" << std::endl;
     }
     stream << "  fu_opcode_in : in  std_logic_vector(16 downto 0);"
            << std::endl
            << "  moves_out    : out std_logic_vector(INSTRUCTIONWIDTH-1 "
               "downto 0));"
            << std::endl
            << std::endl
            << "end rv32_microcode;" << std::endl
            << std::endl
            << "architecture rtl of rv32_microcode is" << std::endl
            << "  signal fu_opcode : std_logic_vector(16 downto 0);"
            << std::endl
            << "  signal moves     : std_logic_vector(INSTRUCTIONWIDTH-1 "
               "downto 0);"
            << std::endl
            << "  constant rs1_start_c : integer := " << rs1BusStart_ << ";"
            << std::endl
            << "  constant rs2_start_c : integer := " << rs2BusStart_ << ";"
            << std::endl
            << "  constant rs1_width_c : integer := " << rs1BusWidth_ << ";"
            << std::endl
            << "  constant rs2_width_c : integer := " << rs2BusWidth_ << ";"
            << std::endl;
     if (hasForwarding_) {
         int len = std::ceil(std::log2(sourceOperationMap_.size()));
         stream << "  signal target_fu : unsigned(" << len << "-1 downto 0);"
                << std::endl;
         stream << "  signal target_fu_r : unsigned (" << len
                << "-1 downto 0);" << std::endl
                << "  signal data_hazard : std_logic;\n"
                << "  signal rs1_hazard : std_logic;\n"
                << "  signal rs2_hazard : std_logic;\n";
     }
  
     stream << std::endl
            << "  begin" << std::endl
            << std::endl
            << "  fu_opcode  <= fu_opcode_in;" << std::endl
            << "  moves_out  <= moves;" << std::endl
            << std::endl;
     if (hasForwarding_) {
         stream << "  data_hazard <= data_hazard_in;" << std::endl
                << "  rs1_hazard  <= rs1_hazard_in;" << std::endl
                << "  rs2_hazard  <= rs2_hazard_in;" << std::endl;
         stream << std::endl;
         generateFUTargetProcess(stream);
     }
     stream << "  process(fu_opcode";
     if (hasForwarding_) {
         stream << ", data_hazard, rs1_hazard, rs2_hazard, target_fu_r";
     }
     stream << ")" << std::endl;
     stream << "  begin" << std::endl;
  
     std::unordered_map<std::string, InstructionBitVector*> instructions =
         constructRInstructions(rs1RFPort_, rs2RFPort_);
     bool firstCond = true;
     for (const auto& op : instructions) {
         if (firstCond) {
             stream << "    if(fu_opcode = \"" << rOperations_.at(op.first)
                    << "\")  then" << std::endl
                    << "      moves <= \"" << op.second->toString() << "\";"
                    << std::endl;
             delete op.second;
             firstCond = false;
             continue;
         }
         stream << "    elsif(fu_opcode(" << rOperations_.at(op.first).size()
                << " - 1 downto 0) = \"" << rOperations_.at(op.first) << "\""
                << ") then" << std::endl
                << "      moves <= \"" << op.second->toString() << "\";"
                << std::endl;
         delete op.second;
     }
  
     instructions = constructIInstructions(rs1RFPort_, rs1RFPort_);
     addBitsToMap(instructions, iOperations_, stream);
  
     instructions = constructSInstructions(rs1RFPort_, rs2RFPort_);
     addBitsToMap(instructions, sOperations_, stream);
  
     instructions = constructBInstructions(rs1RFPort_, rs2RFPort_);
     addBitsToMap(instructions, bOperations_, stream);
  
     instructions = constructUJInstructions();
     addBitsToMap(instructions, ujOperations_, stream);
  
     stream << "    else" << std::endl;
     stream << "      moves <= \"" + NOP_ + "\";" << std::endl;
  
     stream << "    end if;" << std::endl;
  
     if (hasForwarding_) {
         stream << "    if(data_hazard = '1') then\n"
                << "      if(rs1_hazard = '1') then\n";
         addRs1ForwardingConditions(
             rOperations_,
             &ProGe::RV32MicroCodeGenerator::constructRInstructions, stream);
         addRs1ForwardingConditions(
             bOperations_,
             &ProGe::RV32MicroCodeGenerator::constructBInstructions, stream);
         addRs1ForwardingConditions(
             sOperations_,
             &ProGe::RV32MicroCodeGenerator::constructSInstructions, stream);
         addRs1ForwardingConditions(
             iOperations_,
             &ProGe::RV32MicroCodeGenerator::constructIInstructions, stream);
         stream << "      end if;\n"
                << "    if(rs2_hazard = '1') then\n";
         addRs2ForwardingConditions(
             rOperations_,
             &ProGe::RV32MicroCodeGenerator::constructRInstructions, stream);
         addRs2ForwardingConditions(
             bOperations_,
             &ProGe::RV32MicroCodeGenerator::constructBInstructions, stream);
         addRs2ForwardingConditions(
             sOperations_,
             &ProGe::RV32MicroCodeGenerator::constructSInstructions, stream);
         stream << "      end if;\n"
                << "    end if;\n";
     }
  
     stream << "  end process;" << std::endl;
  
     stream << "end architecture rtl;" << std::endl;
  
     stream.close();
 }

References addBitsToMap(), addRs1ForwardingConditions(), addRs2ForwardingConditions(), bOperations_, constructBInstructions(), constructIInstructions(), constructRInstructions(), constructSInstructions(), constructUJInstructions(), FileSystem::DIRECTORY_SEPARATOR, DS, generateFUTargetProcess(), hasForwarding_, iOperations_, NOP_, rOperations_, rs1BusStart_, rs1BusWidth_, rs1RFPort_, rs2BusStart_, rs2BusWidth_, rs2RFPort_, sOperations_, sourceOperationMap_, and ujOperations_.

Referenced by generateRTL().

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◆ generateNOP()

void ProGe::RV32MicroCodeGenerator::generateNOP ( )

private

Definition at line 458 of file RV32MicroCodeGenerator.cc.

                                     {
     CodeCompressorPlugin* compressor = &pig_->compressor();
     Instruction* instruction = new Instruction();
     InstructionBitVector* bits = compressor->bemInstructionBits(*instruction);
     NOP_ = bits->toString();
     delete instruction;
 }

References CodeCompressorPlugin::bemInstructionBits(), ProgramImageGenerator::compressor(), NOP_, pig_, and BitVector::toString().

Referenced by RV32MicroCodeGenerator().

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◆ generateOperationLatencyLogic()

std::string ProGe::RV32MicroCodeGenerator::generateOperationLatencyLogic ( HDLTemplateInstantiator & instantiator )

private

Definition at line 1278 of file RV32MicroCodeGenerator.cc.

                                            {
     std::map<std::string, std::string> operations;
     operations.insert(rOperations_.begin(), rOperations_.end());
     int maxVal = 1;
     for (const auto& op : iOperations_) {
         if (!rOperations_.count(op.first)) {
             operations.insert(op);
         }
     }
     std::map<std::string, int> opLatency;
     for (const auto& op : operations) {
         FunctionUnit* fu = mapFunctionUnit(op.first);
         HWOperation* operation = fu->operation(op.first);
         if (operation->latency() > 1) {
             opLatency.insert({op.first, operation->latency() - 1});
             if (operation->latency() > maxVal) {
                 maxVal = operation->latency();
             }
         }
     }
     int len = std::ceil(std::log2((maxVal)) + 1);
     instantiator.replacePlaceholder("op-lat-width", std::to_string(len));
     if (opLatency.size() == 0) {
         return "op_latency <= to_unsigned(0,op_lat_width_c);";
     }
     variableLengthOpLatency_ = true;
     std::string logic =
         "process(fu_opcode)\n"
         "begin\n";
     bool firstCond = true;
     for (const auto& op : opLatency) {
         std::string cond = "  elsif ";
         if (firstCond) {
             cond = "  if ";
             firstCond = false;
         }
         if (rOperations_.count(op.first) && iOperations_.count(op.first)) {
             cond += "fu_opcode = \"" + rOperations_.at(op.first) + "\" or " +
                     "fu_opcode(" +
                     std::to_string(iOperations_.at(op.first).size()) +
                     "-1 downto 0) = \"" + iOperations_.at(op.first) +
                     "\" then\n";
         } else {
             cond += "fu_opcode(" +
                     std::to_string(operations.at(op.first).size()) +
                     "-1 downto 0) =  \"" + operations.at(op.first) +
                     "\" then\n";
         }
         logic += cond + "     op_latency <= to_unsigned(" +
                  std::to_string(op.second) + ",op_lat_width_c);\n";
     }
     logic +=
         "  else\n"
         "    op_latency <= to_unsigned(0,op_lat_width_c);\n"
         "  end if;\n"
         "end process;\n";
     return logic;
 }

References iOperations_, TTAMachine::HWOperation::latency(), mapFunctionUnit(), TTAMachine::FunctionUnit::operation(), HDLTemplateInstantiator::replacePlaceholder(), rOperations_, and variableLengthOpLatency_.

Referenced by generateWrapper().

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◆ generateRTL()

void ProGe::RV32MicroCodeGenerator::generateRTL	(	HDLTemplateInstantiator &	instantiator,
		const std::string &	fileDst
	)

virtual

Implements ProGe::MicroCodeGenerator.

Definition at line 1556 of file RV32MicroCodeGenerator.cc.

                                                                      {
     generateMap(fileDst);
     generateWrapper(instantiator, fileDst);
 }

References generateMap(), and generateWrapper().

Referenced by DefaultICDecoderGenerator::generate().

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◆ generateWrapper()

void ProGe::RV32MicroCodeGenerator::generateWrapper	(	HDLTemplateInstantiator &	instantiator,
		const std::string &	fileDst
	)

private

Definition at line 1339 of file RV32MicroCodeGenerator.cc.

                                                                      {
     instantiator.replacePlaceholder(
         "rs1-bus-width", std::to_string(rs1BusWidth_));
     instantiator.replacePlaceholder(
         "rs2-bus-width", std::to_string(rs2BusWidth_));
     instantiator.replacePlaceholder(
         "rd-bus-width", std::to_string(rdBusWidth_));
     instantiator.replacePlaceholder(
         "simm-bus-width", std::to_string(simmBusWidth_));
  
     instantiator.replacePlaceholder(
         "rs1-bus-start", std::to_string(rs1BusStart_));
     instantiator.replacePlaceholder(
         "rs2-bus-start", std::to_string(rs2BusStart_));
     instantiator.replacePlaceholder(
         "rd-bus-start", std::to_string(rdBusStart_));
     instantiator.replacePlaceholder(
         "simm-bus-start", std::to_string(simmBusStart_));
  
     instantiator.replacePlaceholder(
         "rs1-rf-start", std::to_string(rs1RFStart_));
     instantiator.replacePlaceholder(
         "rs2-rf-start", std::to_string(rs2RFStart_));
     instantiator.replacePlaceholder(
         "rd-rf-start", std::to_string(rdRFStart_));
     instantiator.replacePlaceholder(
         "simm-rf-start", std::to_string(simmRFStart_));
  
     if (eVariant_) {
         instantiator.replacePlaceholder("rf-width", std::to_string(4));
     } else {
         instantiator.replacePlaceholder("rf-width", std::to_string(5));
     }
  
     std::string nop = NOP_;
     reverse(nop.begin(), nop.end());
     nop = nop.substr(rdBusStart_, rdBusWidth_);
     reverse(nop.begin(), nop.end());
     const std::string rdNOP = nop;
  
     instantiator.replacePlaceholder("rd-nop", rdNOP);
     instantiator.replacePlaceholder("nop-instruction", NOP_);
     instantiator.replacePlaceholder(
         "rv32-microcode-simm-assign", "simm_out <= simm_r;");
  
     const std::string DS = FileSystem::DIRECTORY_SEPARATOR;
     const std::string templateDir = Environment::dataDirPath("ProGe");
  
     instantiator.replacePlaceholder(
         "rv32-microcode-instruction-assign",
         "instruction <= instruction_in;");
  
     if (hasForwarding_) {
         std::string forwardingPorts =
             "  clk            : in std_logic;\n"
             "  rstx           : in std_logic;\n"
             "  glock_in       : in std_logic;\n"
             "  data_hazard_in : in std_logic;\n"
             "  rs1_hazard_in  : in std_logic;\n"
             "  rs2_hazard_in  : in std_logic;\n"
             "  halt           : in std_logic;\n";
  
         std::string forwardingPortMapping =
             "clk              => clk,\n"
             "rstx             => rstx,\n"
             "glock_in         => glock_in,\n"
             "data_hazard_in   => data_hazard,\n"
             "rs1_hazard_in    => rs1_hazard,\n"
             "rs2_hazard_in    => rs2_hazard,\n"
             "halt             => filling_instruction_pipeline,";
  
         instantiator.replacePlaceholder("forwarding-ports", forwardingPorts);
         instantiator.replacePlaceholder(
             "forwarding-port-mapping", forwardingPortMapping);
     } else {
         instantiator.replacePlaceholder(
             "data-hazard-stall", "and data_hazard = '0'");
         instantiator.replacePlaceholder(
             "data-hazard-assign-conds",
             "elsif(data_hazard_r = '1') then\n"
             "  data_hazard <= '0';");
         instantiator.replacePlaceholder(
             "data-hazard-detection-sensitivity-list-signals",
             ", data_hazard_r");
     }
     instantiator.replacePlaceholder(
         "rv32-microcode-op-latency-process",
         generateOperationLatencyLogic(instantiator));
     std::string otherStates;
  
     if (variableLengthOpLatency_) {
         otherStates += ",HANDLE_OP_LATENCY";
     }
     if (!bypassInstructionRegister_) {
         otherStates += ",FILL_INSTRUCTION_PIPELINE_2";
     }
     instantiator.replacePlaceholder(
         "rv32-microcode-other-states", otherStates);
     std::string executeLogic;
     std::string fsm_sensitivity_list_signals;
     executeLogic =
         "  if(glock_in = '1') then\n"
         "    bubble <= '1';\n"
         "    stall_ifetch <= '0';\n"
         "    NS <= EXECUTE;\n"
         "  elsif (rv_jump_wire = '1' or rv_auipc_wire = '1') then\n"
         "     rd_bus_move <= rd_move;\n"
         "     stall_ifetch <= '0';\n"
         "     bubble <= '1';\n"
         "     if rv_auipc_wire = '0' then\n"
         "       NS <= FILL_INSTRUCTION_PIPELINE;\n"
         "     end if;\n";
     if (!hasForwarding_) {
         fsm_sensitivity_list_signals = ", data_hazard";
         if (variableLengthOpLatency_) {
             executeLogic +=
                 "  elsif(op_latency_stall = '1' and data_hazard = '0') then\n"
                 "    bubble <= '0';\n"
                 "    NS <= HANDLE_OP_LATENCY;\n"
                 "    stall_ifetch <= '1';\n"
                 "    rd_bus_move <= rd_nop_c;\n";
         }
         executeLogic +=
             "  elsif(data_hazard = '1') then\n"
             "    bubble <= '1';\n"
             "    rd_bus_move <= rd_nop_c;\n"
             "    stall_ifetch <= '1';\n"
             "    NS <= EXECUTE;\n"
             "  elsif (is_control_flow_op = '1') then\n"
             "    bubble <= '0';\n"
             "    stall_ifetch <= '1';\n"
             "    NS <= HANDLE_CONTROL_FLOW_OP;\n"
             "    handle_control_flow_ns <= '1';\n"
             "  else\n"
             "    bubble <= '0';\n"
             "    stall_ifetch <= '0';\n"
             "    NS <= EXECUTE;\n"
             "  end if;\n";
     } else {
         if (variableLengthOpLatency_) {
             executeLogic +=
                 "  elsif(op_latency_stall = '1') then\n"
                 "    bubble <= '0';\n"
                 "    NS <= HANDLE_OP_LATENCY;\n"
                 "    stall_ifetch <= '1';\n"
                 "    rd_bus_move <= rd_nop_c;\n";
         }
         executeLogic +=
             "  elsif (is_control_flow_op = '1') then\n"
             "    bubble <= '0';\n"
             "    stall_ifetch <= '1';\n"
             "    NS <= HANDLE_CONTROL_FLOW_OP;\n"
             "    handle_control_flow_ns <= '1';\n"
             "  else\n"
             "    bubble <= '0';\n"
             "    stall_ifetch <= '0';\n"
             "    NS <= EXECUTE;\n"
             "  end if;\n";
     }
     if (variableLengthOpLatency_) {
         fsm_sensitivity_list_signals += ",  op_latency_stall";
         executeLogic +=
             "\n"
             "when HANDLE_OP_LATENCY =>\n"
             "  bubble <= '1';\n"
             "  stall_ifetch <= '1';\n"
             "  rd_bus_move <= rd_nop_c;\n"
             "  NS <= HANDLE_OP_LATENCY;\n"
             "  if(op_latency_stall = '0') then\n"
             "    NS <= EXECUTE;\n"
             "    stall_ifetch <= '0';\n"
             "    rd_bus_move <= rd_move;\n"
             "  end if;";
     }
     std::string instructionPipelineStates;
     if (bypassInstructionRegister_) {
         instructionPipelineStates =
             "when FILL_INSTRUCTION_PIPELINE =>\n"
             "  filling_instruction_pipeline <= '1';\n"
             "  bubble <= '1';\n"
             "  rd_bus_move <= rd_nop_c;\n"
             "  stall_ifetch <= '0';\n"
             "  NS <= EXECUTE;\n";
     } else {
         instructionPipelineStates =
             "when FILL_INSTRUCTION_PIPELINE =>\n"
             "  filling_instruction_pipeline <= '1';\n"
             "  bubble <= '1';\n"
             "  rd_bus_move <= rd_nop_c;\n"
             "  stall_ifetch <= '0';\n"
             "  NS <= FILL_INSTRUCTION_PIPELINE_2;\n"
             "\n"
             "\n"
             "when FILL_INSTRUCTION_PIPELINE_2 =>\n"
             "  filling_instruction_pipeline <= '1';\n"
             "  bubble <= '1';\n"
             "  rd_bus_move <= rd_nop_c;\n"
             "  stall_ifetch <= '0';\n"
             "  NS <= EXECUTE;\n"
             "\n";
     }
     instantiator.replacePlaceholder(
         "rv32-microcode-instruction-pipeline-logic",
         instructionPipelineStates);
  
     instantiator.replacePlaceholder(
         "rv32-microcode-fsm-sensitivity-list-signals",
         fsm_sensitivity_list_signals);
     instantiator.replacePlaceholder(
         "rv32-microcode-execute-logic", executeLogic);
     instantiator.instantiateTemplateFile(
         templateDir + DS + "rv32_microcode_wrapper.vhdl.tmpl",
         fileDst + DS + "rv32_microcode_wrapper.vhdl");
 }

References bypassInstructionRegister_, Environment::dataDirPath(), FileSystem::DIRECTORY_SEPARATOR, DS, eVariant_, generateOperationLatencyLogic(), hasForwarding_, HDLTemplateInstantiator::instantiateTemplateFile(), NOP_, rdBusStart_, rdBusWidth_, rdRFStart_, HDLTemplateInstantiator::replacePlaceholder(), rs1BusStart_, rs1BusWidth_, rs1RFStart_, rs2BusStart_, rs2BusWidth_, rs2RFStart_, simmBusStart_, simmBusWidth_, simmRFStart_, and variableLengthOpLatency_.

Referenced by generateRTL().

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◆ initializeOperations()

void ProGe::RV32MicroCodeGenerator::initializeOperations ( )

private

Definition at line 139 of file RV32MicroCodeGenerator.cc.

                                              {
     for (int i = 0; i < bem_->instructionFormatCount(); i++) {
         InstructionFormat fTemp = bem_->instructionFormat(i);
         std::map<std::string, int> ops = fTemp.operations();
         for (const auto& op : ops) {
             std::string name = op.first;
             int encoding = op.second;
             BitVector bits = BitVector();
             if (fTemp.name() == "riscv_r_type") {
                 bits.pushBack(encoding, 17);
                 std::string encBits = bits.toString();
                 if (MapTools::containsKey(operationNameTable, name)) {
                     const std::string tceOpName = operationNameTable.at(name);
                     rOperations_.insert({tceOpName, encBits});
                 } else {
                     rOperations_.insert({name, encBits});
                 }
             } else if (fTemp.name() == "riscv_i_type") {
                 std::string encBits;
                 // Shift operations use imm bits for opcode
                 if (name == "srai" || name == "slli" || name == "srli") {
                     bits.pushBack(encoding, 17);
                     encBits = bits.toString();
                 } else {
                     bits.pushBack(encoding, 10);
                     encBits = bits.toString();
                 }
                 if (MapTools::containsKey(operationNameTable, name)) {
                     const std::string tceOpName = operationNameTable.at(name);
                     iOperations_.insert({tceOpName, encBits});
                 } else {
                     iOperations_.insert({name, encBits});
                 }
             } else if (fTemp.name() == "riscv_s_type") {
                 bits.pushBack(encoding, 10);
                 std::string encBits = bits.toString();
                 if (MapTools::containsKey(operationNameTable, name)) {
                     const std::string tceOpName = operationNameTable.at(name);
                     sOperations_.insert({tceOpName, encBits});
                 } else {
                     sOperations_.insert({name, encBits});
                 }
             } else if (fTemp.name() == "riscv_b_type") {
                 bits.pushBack(encoding, 10);
                 std::string encBits = bits.toString();
                 if (MapTools::containsKey(operationNameTable, name)) {
                     const std::string tceOpName = operationNameTable.at(name);
                     bOperations_.insert(
                         {operationNameTable.at(name), encBits});
                 } else {
                     bOperations_.insert({name, encBits});
                 }
             } else if (fTemp.name() == "riscv_u_type") {
                 bits.pushBack(encoding, 7);
                 std::string encBits = bits.toString();
                 if (MapTools::containsKey(operationNameTable, name)) {
                     const std::string tceOpName = operationNameTable.at(name);
                     ujOperations_.insert({tceOpName, encBits});
                 } else {
                     ujOperations_.insert({name, encBits});
                 }
             } else if (fTemp.name() == "riscv_j_type") {
                 bits.pushBack(encoding, 7);
                 std::string encBits = bits.toString();
                 if (MapTools::containsKey(operationNameTable, name)) {
                     const std::string tceOpName = operationNameTable.at(name);
                     ujOperations_.insert({tceOpName, encBits});
                 } else {
                     ujOperations_.insert({name, encBits});
                 }
             }
         }
     }
 }

References bem_, bOperations_, MapTools::containsKey(), BinaryEncoding::instructionFormat(), BinaryEncoding::instructionFormatCount(), iOperations_, InstructionFormat::name(), operationNameTable, InstructionFormat::operations(), BitVector::pushBack(), rOperations_, sOperations_, BitVector::toString(), and ujOperations_.

Referenced by RV32MicroCodeGenerator().

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◆ mapFunctionUnit()

FunctionUnit * ProGe::RV32MicroCodeGenerator::mapFunctionUnit ( const std::string & operation ) const

private

Definition at line 245 of file RV32MicroCodeGenerator.cc.

                                                                         {
     Machine::FunctionUnitNavigator fuNav = machine_->functionUnitNavigator();
     for (int i = 0; i < fuNav.count(); i++) {
         FunctionUnit* fu = fuNav.item(i);
         if (fu->hasOperation(operation)) {
             return fu;
         }
     }
     if (machine_->controlUnit()->hasOperation(operation)) {
         return static_cast<FunctionUnit*>(machine_->controlUnit());
     }
     throwOperationNotFoundError(operation);
     return NULL;
 }

References TTAMachine::Machine::controlUnit(), TTAMachine::Machine::Navigator< ComponentType >::count(), TTAMachine::Machine::functionUnitNavigator(), TTAMachine::FunctionUnit::hasOperation(), TTAMachine::Machine::Navigator< ComponentType >::item(), machine_, and throwOperationNotFoundError().

Referenced by addBPorts(), addIPorts(), addRPorts(), addSPorts(), addUJPorts(), constructBInstructions(), constructIInstructions(), constructRInstructions(), constructSInstructions(), constructUJInstructions(), and generateOperationLatencyLogic().

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◆ operationPorts()

std::set< Port * > ProGe::RV32MicroCodeGenerator::operationPorts ( const std::unordered_map< std::string, BaseFUPort * > & ports ) const

private

Definition at line 603 of file RV32MicroCodeGenerator.cc.

                                                                  {
     std::set<Port*> retval;
     for (const auto& op : ports) {
         retval.insert(static_cast<Port*>(op.second));
     }
     return retval;
 }

Referenced by findConnectedBusses().

◆ setBypassInstructionRegister()

void ProGe::RV32MicroCodeGenerator::setBypassInstructionRegister ( const bool & value )

Definition at line 1563 of file RV32MicroCodeGenerator.cc.

                                                                       {
     bypassInstructionRegister_ = value;
 }

References bypassInstructionRegister_.

Referenced by DefaultICDecoderGenerator::generate().

◆ throwInputPortError()

void ProGe::RV32MicroCodeGenerator::throwInputPortError	(	const BaseFUPort *	port,
		const std::string &	type
	)		const

private

Definition at line 278 of file RV32MicroCodeGenerator.cc.

                                                          {
     std::string fuName = port->parentUnit()->name();
     std::string msg = type + " operand port \'" + port->name() +
                       "\' in FU \'" + fuName + "\' not mapped as input";
     throw InvalidData(__FILE__, __LINE__, __func__, msg);
 }

References __func__, TTAMachine::Port::name(), TTAMachine::Component::name(), and TTAMachine::BaseFUPort::parentUnit().

Referenced by addBPorts(), addRPorts(), and addSPorts().

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◆ throwOperandCountError()

void ProGe::RV32MicroCodeGenerator::throwOperandCountError	(	const std::string &	op,
		int	required,
		int	found
	)		const

private

Definition at line 296 of file RV32MicroCodeGenerator.cc.

                                                         {
     std::string msg = "Operation " + op +
                       " has invalid amount of operands. " +
                       std::to_string(required) + " required, " +
                       std::to_string(found) + " found.";
     throw InvalidData(__FILE__, __LINE__, __func__, msg);
 }

References __func__.

Referenced by addBPorts(), addIPorts(), addRPorts(), and addSPorts().

◆ throwOperationNotFoundError()

void ProGe::RV32MicroCodeGenerator::throwOperationNotFoundError ( const std::string & op ) const

private

Definition at line 261 of file RV32MicroCodeGenerator.cc.

                                {
     std::string msg = "Cannot find operation '" + op + "\' in machine.";
     throw InvalidData(__FILE__, __LINE__, __func__, msg);
 }

References __func__.

Referenced by mapFunctionUnit(), and validateOperations().

◆ throwOutputPortError()

void ProGe::RV32MicroCodeGenerator::throwOutputPortError	(	const BaseFUPort *	port,
		const std::string &	type
	)		const

private

Definition at line 287 of file RV32MicroCodeGenerator.cc.

                                                          {
     std::string fuName = port->parentUnit()->name();
     std::string msg = type + " operand port \'" + port->name() +
                       "\' in FU \'" + fuName + "\' not mapped as output";
     throw InvalidData(__FILE__, __LINE__, __func__, msg);
 }

References __func__, TTAMachine::Port::name(), TTAMachine::Component::name(), and TTAMachine::BaseFUPort::parentUnit().

Referenced by addIPorts(), addRPorts(), and addUJPorts().

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◆ throwTriggeringPortError()

void ProGe::RV32MicroCodeGenerator::throwTriggeringPortError	(	const BaseFUPort *	port,
		const std::string &	type
	)		const

private

Definition at line 268 of file RV32MicroCodeGenerator.cc.

                                                          {
     std::string fuName = port->parentUnit()->name();
     std::string msg = type + " operand port \'" + port->name() +
                       "\' in FU \'" + fuName +
                       "\' not mapped as triggering port";
     throw InvalidData(__FILE__, __LINE__, __func__, msg);
 }

References __func__, TTAMachine::Port::name(), TTAMachine::Component::name(), and TTAMachine::BaseFUPort::parentUnit().

Referenced by addBPorts(), addRPorts(), addSPorts(), and addUJPorts().

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◆ validateOperations()

void ProGe::RV32MicroCodeGenerator::validateOperations ( ) const

private

Definition at line 215 of file RV32MicroCodeGenerator.cc.

                                                  {
     for (const auto& op : sOperations_) {
         const std::string opName = op.first;
         if (!machine_->hasOperation(opName)) {
             throwOperationNotFoundError(opName);
         }
     }
     for (const auto& op : bOperations_) {
         const std::string opName = op.first;
         if (!machine_->hasOperation(opName)) {
             throwOperationNotFoundError(opName);
         }
     }
     for (const auto& op : ujOperations_) {
         const std::string opName = op.first;
         if (op.first != "move") {
             if (!machine_->hasOperation(opName)) {
                 throwOperationNotFoundError(opName);
             }
         }
     }
     for (const auto& op : rOperations_) {
         const std::string opName = op.first;
         if (!machine_->hasOperation(opName)) {
             throwOperationNotFoundError(opName);
         }
     }
 }

References bOperations_, TTAMachine::Machine::hasOperation(), machine_, rOperations_, sOperations_, throwOperationNotFoundError(), and ujOperations_.

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Member Data Documentation

◆ bem_

const BinaryEncoding* ProGe::RV32MicroCodeGenerator::bem_

private

Definition at line 179 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and initializeOperations().

◆ bOperations_

std::map<std::string, std::string> ProGe::RV32MicroCodeGenerator::bOperations_

private

Definition at line 112 of file RV32MicroCodeGenerator.hh.

Referenced by constructBInstructions(), findOperationPorts(), generateFUTargetProcess(), generateMap(), initializeOperations(), and validateOperations().

◆ busses_

std::vector<Bus*> ProGe::RV32MicroCodeGenerator::busses_

private

Definition at line 180 of file RV32MicroCodeGenerator.hh.

Referenced by findConnectedBusses(), and RV32MicroCodeGenerator().

◆ bypassInstructionRegister_

bool ProGe::RV32MicroCodeGenerator::bypassInstructionRegister_

private

Definition at line 213 of file RV32MicroCodeGenerator.hh.

Referenced by generateWrapper(), and setBypassInstructionRegister().

◆ eVariant_

bool ProGe::RV32MicroCodeGenerator::eVariant_

private

Definition at line 216 of file RV32MicroCodeGenerator.hh.

Referenced by findRF(), and generateWrapper().

◆ hasForwarding_

bool ProGe::RV32MicroCodeGenerator::hasForwarding_

private

Definition at line 214 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), generateMap(), generateWrapper(), and RV32MicroCodeGenerator().

◆ iOperations_

std::map<std::string, std::string> ProGe::RV32MicroCodeGenerator::iOperations_

private

Definition at line 110 of file RV32MicroCodeGenerator.hh.

Referenced by addRs1ForwardingConditions(), constructIInstructions(), findOperationPorts(), generateFUTargetProcess(), generateMap(), generateOperationLatencyLogic(), and initializeOperations().

◆ machine_

const Machine* ProGe::RV32MicroCodeGenerator::machine_

private

Definition at line 178 of file RV32MicroCodeGenerator.hh.

Referenced by addIPorts(), findRF(), mapFunctionUnit(), and validateOperations().

◆ NOP_

std::string ProGe::RV32MicroCodeGenerator::NOP_

private

Definition at line 212 of file RV32MicroCodeGenerator.hh.

Referenced by generateMap(), generateNOP(), and generateWrapper().

◆ pig_

ProgramImageGenerator* ProGe::RV32MicroCodeGenerator::pig_

private

Definition at line 210 of file RV32MicroCodeGenerator.hh.

Referenced by constructBInstructions(), constructIInstructions(), constructRInstructions(), constructSInstructions(), constructUJInstructions(), generateNOP(), RV32MicroCodeGenerator(), and ~RV32MicroCodeGenerator().

◆ rdBus_

Bus* ProGe::RV32MicroCodeGenerator::rdBus_

private

Definition at line 202 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), constructIInstructions(), constructRInstructions(), constructUJInstructions(), and findBusWidths().

◆ rdBusStart_

int ProGe::RV32MicroCodeGenerator::rdBusStart_

private

Definition at line 191 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ rdBusWidth_

int ProGe::RV32MicroCodeGenerator::rdBusWidth_

private

Definition at line 186 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ rdPorts_

std::unordered_map<std::string, BaseFUPort*> ProGe::RV32MicroCodeGenerator::rdPorts_

private

Definition at line 82 of file RV32MicroCodeGenerator.hh.

Referenced by addIPorts(), addRPorts(), addUJPorts(), constructIInstructions(), constructRInstructions(), constructUJInstructions(), findConnectedBusses(), and findOperationSources().

◆ rdRFPort_

RFPort* ProGe::RV32MicroCodeGenerator::rdRFPort_

private

Definition at line 208 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), constructIInstructions(), constructRInstructions(), and constructUJInstructions().

◆ rdRFStart_

int ProGe::RV32MicroCodeGenerator::rdRFStart_

private

Definition at line 197 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ RF_

RegisterFile* ProGe::RV32MicroCodeGenerator::RF_

private

Definition at line 182 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), and findRF().

◆ rOperations_

std::map<std::string, std::string> ProGe::RV32MicroCodeGenerator::rOperations_

private

Definition at line 109 of file RV32MicroCodeGenerator.hh.

Referenced by addIPorts(), addRs1ForwardingConditions(), constructRInstructions(), findOperationPorts(), generateFUTargetProcess(), generateMap(), generateOperationLatencyLogic(), initializeOperations(), and validateOperations().

◆ rs1Bus_

Bus* ProGe::RV32MicroCodeGenerator::rs1Bus_

private

Definition at line 200 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), constructBInstructions(), constructIInstructions(), constructRInstructions(), constructSInstructions(), constructUJInstructions(), and findBusWidths().

◆ rs1BusStart_

int ProGe::RV32MicroCodeGenerator::rs1BusStart_

private

Definition at line 189 of file RV32MicroCodeGenerator.hh.

Referenced by addRs1ForwardingConditions(), findBusWidths(), generateMap(), and generateWrapper().

◆ rs1BusWidth_

int ProGe::RV32MicroCodeGenerator::rs1BusWidth_

private

Definition at line 184 of file RV32MicroCodeGenerator.hh.

Referenced by addRs1ForwardingConditions(), findBusWidths(), generateMap(), and generateWrapper().

◆ rs1Ports_

std::unordered_map<std::string, BaseFUPort*> ProGe::RV32MicroCodeGenerator::rs1Ports_

private

Definition at line 80 of file RV32MicroCodeGenerator.hh.

Referenced by addBPorts(), addIPorts(), addRPorts(), addSPorts(), constructBInstructions(), constructIInstructions(), constructRInstructions(), constructSInstructions(), constructUJInstructions(), and findConnectedBusses().

◆ rs1RFPort_

RFPort* ProGe::RV32MicroCodeGenerator::rs1RFPort_

private

Definition at line 206 of file RV32MicroCodeGenerator.hh.

Referenced by addRs2ForwardingConditions(), connectRF(), constructUJInstructions(), and generateMap().

◆ rs1RFStart_

int ProGe::RV32MicroCodeGenerator::rs1RFStart_

private

Definition at line 195 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ rs2Bus_

Bus* ProGe::RV32MicroCodeGenerator::rs2Bus_

private

Definition at line 201 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), constructBInstructions(), constructRInstructions(), constructSInstructions(), and findBusWidths().

◆ rs2BusStart_

int ProGe::RV32MicroCodeGenerator::rs2BusStart_

private

Definition at line 190 of file RV32MicroCodeGenerator.hh.

Referenced by addRs2ForwardingConditions(), findBusWidths(), generateMap(), and generateWrapper().

◆ rs2BusWidth_

int ProGe::RV32MicroCodeGenerator::rs2BusWidth_

private

Definition at line 185 of file RV32MicroCodeGenerator.hh.

Referenced by addRs2ForwardingConditions(), findBusWidths(), generateMap(), and generateWrapper().

◆ rs2Ports_

std::unordered_map<std::string, BaseFUPort*> ProGe::RV32MicroCodeGenerator::rs2Ports_

private

Definition at line 81 of file RV32MicroCodeGenerator.hh.

Referenced by addBPorts(), addRPorts(), addSPorts(), constructBInstructions(), constructRInstructions(), constructSInstructions(), and findConnectedBusses().

◆ rs2RFPort_

RFPort* ProGe::RV32MicroCodeGenerator::rs2RFPort_

private

Definition at line 207 of file RV32MicroCodeGenerator.hh.

Referenced by addRs1ForwardingConditions(), connectRF(), and generateMap().

◆ rs2RFStart_

int ProGe::RV32MicroCodeGenerator::rs2RFStart_

private

Definition at line 196 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ simmBus_

Bus* ProGe::RV32MicroCodeGenerator::simmBus_

private

Definition at line 203 of file RV32MicroCodeGenerator.hh.

Referenced by connectRF(), constructBInstructions(), constructIInstructions(), constructSInstructions(), constructUJInstructions(), and findBusWidths().

◆ simmBusStart_

int ProGe::RV32MicroCodeGenerator::simmBusStart_

private

Definition at line 192 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ simmBusWidth_

int ProGe::RV32MicroCodeGenerator::simmBusWidth_

private

Definition at line 187 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ simmPorts_

std::unordered_map<std::string, BaseFUPort*> ProGe::RV32MicroCodeGenerator::simmPorts_

private

Definition at line 83 of file RV32MicroCodeGenerator.hh.

Referenced by addBPorts(), addIPorts(), addRPorts(), addSPorts(), addUJPorts(), constructBInstructions(), constructIInstructions(), constructSInstructions(), constructUJInstructions(), and findConnectedBusses().

◆ simmRFStart_

int ProGe::RV32MicroCodeGenerator::simmRFStart_

private

Definition at line 198 of file RV32MicroCodeGenerator.hh.

Referenced by findBusWidths(), and generateWrapper().

◆ sOperations_

std::map<std::string, std::string> ProGe::RV32MicroCodeGenerator::sOperations_

private

Definition at line 111 of file RV32MicroCodeGenerator.hh.

Referenced by constructSInstructions(), findOperationPorts(), generateFUTargetProcess(), generateMap(), initializeOperations(), and validateOperations().

◆ sourceOperationMap_

std::unordered_map<Port*, std::vector<std::string> > ProGe::RV32MicroCodeGenerator::sourceOperationMap_

private

Definition at line 90 of file RV32MicroCodeGenerator.hh.

Referenced by addRs1ForwardingConditions(), addRs2ForwardingConditions(), findOperationSources(), generateFUTargetProcess(), and generateMap().

◆ sourcePortID_

std::unordered_map<Port*, int> ProGe::RV32MicroCodeGenerator::sourcePortID_

private

Definition at line 87 of file RV32MicroCodeGenerator.hh.

Referenced by addRs1ForwardingConditions(), addRs2ForwardingConditions(), and generateFUTargetProcess().

◆ ujOperations_

std::map<std::string, std::string> ProGe::RV32MicroCodeGenerator::ujOperations_

private

Definition at line 113 of file RV32MicroCodeGenerator.hh.

Referenced by constructUJInstructions(), findOperationPorts(), generateFUTargetProcess(), generateMap(), initializeOperations(), and validateOperations().

◆ variableLengthOpLatency_

bool ProGe::RV32MicroCodeGenerator::variableLengthOpLatency_

private

Definition at line 215 of file RV32MicroCodeGenerator.hh.

Referenced by generateOperationLatencyLogic(), and generateWrapper().

The documentation for this class was generated from the following files:

Public Member Functions

Private Member Functions

Private Attributes

Detailed Description

Constructor & Destructor Documentation

◆ RV32MicroCodeGenerator()

◆ ~RV32MicroCodeGenerator()

Member Function Documentation

◆ addBitsToMap()

◆ addBPorts()

◆ addIPorts()

◆ addRPorts()

◆ addRs1ForwardingConditions()

◆ addRs2ForwardingConditions()

◆ addSPorts()

◆ addUJPorts()

◆ connectRF()

◆ constructBInstructions()

◆ constructIInstructions()

◆ constructRInstructions()

◆ constructSInstructions()

◆ constructUJInstructions()

◆ findBusWidths()

◆ findConnectedBusses()

◆ findOperationPorts()

◆ findOperationSources()

◆ findRF()

◆ generateFUTargetProcess()

◆ generateMap()

◆ generateNOP()

◆ generateOperationLatencyLogic()

◆ generateRTL()

◆ generateWrapper()

◆ initializeOperations()

◆ mapFunctionUnit()

◆ operationPorts()

◆ setBypassInstructionRegister()

◆ throwInputPortError()

◆ throwOperandCountError()

◆ throwOperationNotFoundError()

◆ throwOutputPortError()

◆ throwTriggeringPortError()

◆ validateOperations()

Member Data Documentation

◆ bem_

◆ bOperations_

◆ busses_

◆ bypassInstructionRegister_

◆ eVariant_

◆ hasForwarding_

◆ iOperations_

◆ machine_

◆ NOP_

◆ pig_

◆ rdBus_

◆ rdBusStart_

◆ rdBusWidth_

◆ rdPorts_

◆ rdRFPort_

◆ rdRFStart_

◆ RF_

◆ rOperations_

◆ rs1Bus_

◆ rs1BusStart_

◆ rs1BusWidth_

◆ rs1Ports_

◆ rs1RFPort_

◆ rs1RFStart_

◆ rs2Bus_

◆ rs2BusStart_

◆ rs2BusWidth_

◆ rs2Ports_

◆ rs2RFPort_

◆ rs2RFStart_

◆ simmBus_

◆ simmBusStart_

◆ simmBusWidth_

◆ simmPorts_

◆ simmRFStart_

◆ sOperations_