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Public Member Functions | Static Public Member Functions | Private Types | Private Member Functions | Static Private Member Functions | Private Attributes | List of all members
ProGe::VerilogNetlistWriter Class Reference

#include <VerilogNetlistWriter.hh>

Inheritance diagram for ProGe::VerilogNetlistWriter:
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Collaboration diagram for ProGe::VerilogNetlistWriter:
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Public Member Functions

 VerilogNetlistWriter (const BaseNetlistBlock &targetBlock)
 
virtual ~VerilogNetlistWriter ()
 
virtual void write (const std::string &dstDirectory)
 
- Public Member Functions inherited from ProGe::NetlistWriter
 NetlistWriter (const BaseNetlistBlock &targetBlock)
 
virtual ~NetlistWriter ()
 

Static Public Member Functions

static void writeGenericDeclaration (const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
 
static void writePortDeclaration (const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
 

Private Types

typedef boost::graph_traits< Netlist >::vertex_descriptor vertex_descriptor
 
typedef boost::graph_traits< Netlist >::edge_descriptor edge_descriptor
 
typedef boost::graph_traits< Netlist >::out_edge_iterator out_edge_iterator
 

Private Member Functions

void writeNetlistParameterPackage (const std::string &dstDirectory) const
 
std::string netlistParameterPkgName () const
 
void writeBlock (const BaseNetlistBlock &block, const std::string &dstDirectory)
 
void writeSignalDeclarations (const BaseNetlistBlock &block, std::ofstream &stream)
 
void writeSignalAssignments (const BaseNetlistBlock &block, std::ofstream &stream) const
 
void writeComponentDeclarations (const BaseNetlistBlock &block, std::ofstream &stream) const
 
void writePortMappings (const BaseNetlistBlock &block, std::ofstream &stream) const
 
std::string indentation (unsigned int level) const
 
TCEString genericMapStringValue (const TCEString &generic) const
 

Static Private Member Functions

static std::string directionString (Direction direction)
 
static std::string generateIndentation (unsigned int level, const std::string &indentation)
 
static bool isNumber (const std::string &formula)
 
static std::string portSignalName (const NetlistPort &port)
 
static std::string portSignalType (const NetlistPort &port)
 

Private Attributes

int groundWidth_
 Width of the ground signal. More...
 

Additional Inherited Members

- Protected Member Functions inherited from ProGe::NetlistWriter
const BaseNetlistBlock & targetNetlistBlock () const
 

Detailed Description

Writes Verilog files which implement the given netlist.

Definition at line 52 of file VerilogNetlistWriter.hh.

Member Typedef Documentation

◆ edge_descriptor

typedef boost::graph_traits<Netlist>::edge_descriptor ProGe::VerilogNetlistWriter::edge_descriptor
private

Definition at line 74 of file VerilogNetlistWriter.hh.

◆ out_edge_iterator

typedef boost::graph_traits<Netlist>::out_edge_iterator ProGe::VerilogNetlistWriter::out_edge_iterator
private

Definition at line 76 of file VerilogNetlistWriter.hh.

◆ vertex_descriptor

typedef boost::graph_traits<Netlist>::vertex_descriptor ProGe::VerilogNetlistWriter::vertex_descriptor
private

Definition at line 72 of file VerilogNetlistWriter.hh.

Constructor & Destructor Documentation

◆ VerilogNetlistWriter()

ProGe::VerilogNetlistWriter::VerilogNetlistWriter ( const BaseNetlistBlock &  targetBlock)

Constructor. Records the input netlist for which it can generate Verilog.

Parameters
netlistThe input netlist.

Definition at line 68 of file VerilogNetlistWriter.cc.

70  : NetlistWriter(targetBlock), groundWidth_(0) {}

◆ ~VerilogNetlistWriter()

ProGe::VerilogNetlistWriter::~VerilogNetlistWriter ( )
virtual

The destructor.

Definition at line 75 of file VerilogNetlistWriter.cc.

75  {
76 }

Member Function Documentation

◆ directionString()

std::string ProGe::VerilogNetlistWriter::directionString ( Direction  direction)
staticprivate

Returns the string that means the same direction as the given one in Verilog.

Returns
The direction string.

Definition at line 573 of file VerilogNetlistWriter.cc.

573  {
574  switch (direction) {
575  case IN:
576  return "input";
577  case OUT:
578  return "output";
579  case BIDIR:
580  return "inout";
581  }
582  assert(false);
583  // dummy return
584  return "";
585 }

References assert, ProGe::BIDIR, ProGe::IN, and ProGe::OUT.

Referenced by writePortDeclaration().

◆ generateIndentation()

std::string ProGe::VerilogNetlistWriter::generateIndentation ( unsigned int  indentationLevel,
const std::string &  indentation 
)
staticprivate

Generates an indentation string with the given parameters.

Parameters
indentationLevelThe level of indentation.
indentationThe string used as indentation (one level).
Returns
The indentation of the given level.

Definition at line 623 of file VerilogNetlistWriter.cc.

625  {
626 
627  string generatedInd("");
628  for (unsigned int i = 0; i < indentationLevel; i++) {
629  generatedInd += indentation;
630  }
631  return generatedInd;
632 }

References indentation().

Referenced by writeGenericDeclaration(), and writePortDeclaration().

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◆ genericMapStringValue()

TCEString ProGe::VerilogNetlistWriter::genericMapStringValue ( const TCEString &  generic) const
private

Tries to determine whether the string generic needs quot marks for generic mapping

If string literal contains '.', or "__" it cannot be a valid Verilog label (i.e. another generic), thus it needs quotation marks.

Parameters
genericString generic value
Returns
Generic mapping string

Definition at line 676 of file VerilogNetlistWriter.cc.

676  {
677 
678  if (generic.startsWith("\"") && generic.endsWith("\"")) {
679  return generic;
680  }
681  std::vector<TCEString> unallowed;
682  unallowed.push_back(".");
683  unallowed.push_back("__");
684  for (unsigned int i = 0; i < unallowed.size(); i++) {
685  if (generic.find(unallowed.at(i)) != TCEString::npos) {
686  TCEString quoted;
687  quoted << "\"" << generic << "\"";
688  return quoted;
689  }
690  }
691  return generic;
692 }

Referenced by writePortMappings().

◆ indentation()

std::string ProGe::VerilogNetlistWriter::indentation ( unsigned int  level) const
private

Returns a string which makes indetation of the given level.

Parameters
levelThe indentation level.

Definition at line 611 of file VerilogNetlistWriter.cc.

611  {
612  return StringTools::indent(level);
613 }

References StringTools::indent().

Referenced by generateIndentation(), writeBlock(), writeGenericDeclaration(), writePortDeclaration(), writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

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◆ isNumber()

bool ProGe::VerilogNetlistWriter::isNumber ( const std::string &  formula)
staticprivate

Tells whether the given string is a non-negative integer number.

Parameters
formulaThe string.
Returns
True if the given string is a non-negative integer number.

Definition at line 594 of file VerilogNetlistWriter.cc.

594  {
595  int length = formula.length();
596  for (int i = 0; i < length; i++) {
597  if (!isdigit(formula[i])) {
598  return false;
599  }
600  }
601  return true;
602 }

Referenced by portSignalType(), and writePortDeclaration().

◆ netlistParameterPkgName()

std::string ProGe::VerilogNetlistWriter::netlistParameterPkgName ( ) const
private

Returns the name of the netlist parameter package(include file).

Returns
The name.

Definition at line 126 of file VerilogNetlistWriter.cc.

126  {
127  return targetNetlistBlock().moduleName() + "_params";
128 }

References ProGe::BaseNetlistBlock::moduleName(), and ProGe::NetlistWriter::targetNetlistBlock().

Referenced by writeBlock(), and writeNetlistParameterPackage().

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◆ portSignalName()

std::string ProGe::VerilogNetlistWriter::portSignalName ( const NetlistPort &  port)
staticprivate

Returns the name of the signal mapped to the given port.

Parameters
portThe port.

Definition at line 641 of file VerilogNetlistWriter.cc.

641  {
642  const BaseNetlistBlock* parentBlock = &port.parentBlock();
643  if (port.hasStaticValue()) {
644  return "{" + Conversion::toString(port.realWidth()) + "{" +
645  ((port.staticValue().is(StaticSignal::VCC)) ? "1'b1"
646  : "1'b0") +
647  "}}";
648  }
649  return parentBlock->instanceName() + "_" + port.name() +"_wire";
650 }

References ProGe::NetlistPort::hasStaticValue(), ProGe::BaseNetlistBlock::instanceName(), ProGe::StaticSignal::is(), ProGe::NetlistPort::name(), ProGe::NetlistPort::parentBlock(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::staticValue(), Conversion::toString(), and ProGe::StaticSignal::VCC.

Referenced by writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

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◆ portSignalType()

std::string ProGe::VerilogNetlistWriter::portSignalType ( const NetlistPort &  port)
staticprivate

Returns the type of the signal mapped to the given port.

Parameters
portThe port.

Definition at line 659 of file VerilogNetlistWriter.cc.

659  {
660  if (port.dataType() == BIT) {
661  return "";
662  } else {
663  if (port.realWidthAvailable()) {
664  int width = port.realWidth();
665  return "[" + Conversion::toString(width?width-1:0) + ":0]";
666  } else if (isNumber(port.widthFormula()) &&
667  (Conversion::toInt(port.widthFormula()) == 0)) {
668  return "[0:0]";
669  } else {
670  return "[" + port.widthFormula()+"-1: 0]";
671  }
672  }
673 }

References ProGe::BIT, ProGe::NetlistPort::dataType(), isNumber(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::realWidthAvailable(), Conversion::toInt(), Conversion::toString(), and ProGe::NetlistPort::widthFormula().

Referenced by writeSignalDeclarations().

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◆ write()

void ProGe::VerilogNetlistWriter::write ( const std::string &  dstDirectory)
virtual

Generates the Verilog files and writes them to the given directory.

Parameters
dstDirectoryThe destination directory.
Exceptions
IOExceptionIf an IO error occurs.
InvalidDataIf the netlist is invalid.

Implements ProGe::NetlistWriter.

Definition at line 86 of file VerilogNetlistWriter.cc.

86  {
87  const BaseNetlistBlock& block = this->targetNetlistBlock();
88  if (block.netlist().isEmpty()) {
89  string errorMsg = "Empty input netlist block.";
90  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
91  }
92 
93  writeNetlistParameterPackage(dstDirectory);
94  writeBlock(block, dstDirectory);
95 }

References __func__, ProGe::Netlist::isEmpty(), ProGe::BaseNetlistBlock::netlist(), ProGe::NetlistWriter::targetNetlistBlock(), writeBlock(), and writeNetlistParameterPackage().

Referenced by ProGe::BaseNetlistBlock::writeSelf().

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◆ writeBlock()

void ProGe::VerilogNetlistWriter::writeBlock ( const BaseNetlistBlock &  block,
const std::string &  dstDirectory 
)
private

Writes the given block of the netlist to the given destination directory.

Parameters
blockThe netlist block.
dstDirectoryThe destination directory.
Exceptions
IOExceptionIf the file cannot be created.

Definition at line 139 of file VerilogNetlistWriter.cc.

140  {
141  string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
142  block.moduleName() + ".v";
143  if (!FileSystem::fileIsCreatable(fileName) &&
144  !(FileSystem::fileExists(fileName) &&
145  FileSystem::fileIsWritable(fileName))) {
146 
147  string errorMsg = "Unable to create file: " + fileName;
148  throw IOException(__FILE__, __LINE__, __func__, errorMsg);
149  }
150 
151  const string entityName = block.moduleName();
152 
153  ofstream outFile;
154  outFile.open(fileName.c_str(), ofstream::out);
155 
156  // create module
157  outFile << "module " + entityName << endl;
158 
159  //create include
160  string separator;
161  outFile << "#(" << endl;
162  if (block.netlist().parameterCount() > 0) {
163  outFile << "`include \"" << netlistParameterPkgName() << "_pkg.vh\""
164  << endl;
165  separator = ",";
166  }
167 
168  for (size_t i = 0; i < block.packageCount(); i++) {
169  outFile << separator << endl;
170  outFile << "`include \"" << block.package(i) << "_pkg.vh\"" << endl;
171  separator = ",";
172  }
173 
174  outFile << ")" << endl;
175 
176  // create port declarations
177  writePortDeclaration(block, 1, indentation(1), outFile);
178  outFile << endl;
179 
180  // create generics
181  writeGenericDeclaration(block, 1, indentation(1), outFile);
182  // create architecture
183  writeSignalDeclarations(block, outFile);
184  outFile << endl;
185  writeSignalAssignments(block, outFile);
186  outFile << endl;
187  writePortMappings(block, outFile);
188  outFile << "endmodule" << endl;
189  outFile << endl;
190  outFile.close();
191 }

References __func__, FileSystem::DIRECTORY_SEPARATOR, FileSystem::fileExists(), FileSystem::fileIsCreatable(), FileSystem::fileIsWritable(), indentation(), ProGe::BaseNetlistBlock::moduleName(), ProGe::BaseNetlistBlock::netlist(), netlistParameterPkgName(), ProGe::BaseNetlistBlock::package(), ProGe::BaseNetlistBlock::packageCount(), ProGe::Netlist::parameterCount(), writeGenericDeclaration(), writePortDeclaration(), writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

Referenced by write().

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◆ writeComponentDeclarations()

void ProGe::VerilogNetlistWriter::writeComponentDeclarations ( const BaseNetlistBlock &  block,
std::ofstream &  stream 
) const
private

◆ writeGenericDeclaration()

void ProGe::VerilogNetlistWriter::writeGenericDeclaration ( const BaseNetlistBlock &  block,
unsigned int  indentationLevel,
const std::string &  indentation,
std::ostream &  stream 
)
static

Writes the generic(parameter) declarations of the given netlist block.

Parameters
blockThe netlist block.
indentationLevelThe indentation level where the generic declaration is written.
indentationThe string used as indentation (one level).
streamThe stream to write.

Definition at line 203 of file VerilogNetlistWriter.cc.

205  {
206  if (block.parameterCount() > 0) {
207  stream << endl;
208  for (size_t i = 0; i < block.parameterCount(); i++) {
209  stream << generateIndentation(indentationLevel, indentation)
210  << "parameter ";
211  Parameter param = block.parameter(i);
212  stream << generateIndentation(indentationLevel + 1, indentation)
213  << param.name();
214  if (param.defaultValue() != "") {
215  stream << " = ";
216  if (param.type().lower() == PARAM_STRING) {
217  // string literal needs quot. marks
218  if (!param.defaultValue().startsWith("\""))
219  stream << "\"";
220  stream << param.defaultValue();
221  if (!param.defaultValue().endsWith("\"")) stream << "\"";
222  } else {
223  stream << param.defaultValue();
224  }
225  }
226  stream << ";" << endl;
227  }
228  }
229 }

References ProGe::Parameter::defaultValue(), TCEString::endsWith(), generateIndentation(), indentation(), TCEString::lower(), ProGe::Parameter::name(), PARAM_STRING, ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), TCEString::startsWith(), and ProGe::Parameter::type().

Referenced by writeBlock().

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◆ writeNetlistParameterPackage()

void ProGe::VerilogNetlistWriter::writeNetlistParameterPackage ( const std::string &  dstDirectory) const
private

Writes the package(include files for verilog) that defines parameters of the netlist.

Parameters
dstDirectoryThe destination directory.

Definition at line 104 of file VerilogNetlistWriter.cc.

105  {
106  string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
107  netlistParameterPkgName() + "_pkg.vh";
108  ofstream outFile;
109  outFile.open(fileName.c_str(), ofstream::out);
110  for (size_t i = 0; i < targetNetlistBlock().netlist().parameterCount();
111  i++) {
112  Parameter param = targetNetlistBlock().netlist().parameter(i);
113  outFile << "parameter " << param.name() << " = " << param.value();
114  if (i != targetNetlistBlock().netlist().parameterCount() - 1)
115  outFile << ",";
116  outFile << endl;
117  }
118 }

References FileSystem::DIRECTORY_SEPARATOR, ProGe::Parameter::name(), ProGe::BaseNetlistBlock::netlist(), netlistParameterPkgName(), ProGe::Netlist::parameter(), ProGe::Netlist::parameterCount(), ProGe::NetlistWriter::targetNetlistBlock(), and ProGe::Parameter::value().

Referenced by write().

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◆ writePortDeclaration()

void ProGe::VerilogNetlistWriter::writePortDeclaration ( const BaseNetlistBlock &  block,
unsigned int  indentationLevel,
const std::string &  indentation,
std::ostream &  stream 
)
static

Writes the port declaration of the given netlist block.

Parameters
blockThe netlist block.
indentationLevelThe indentation level where the generic declaration is written.
indentationThe string used as indentation (one level).
streamThe stream to write.

Definition at line 241 of file VerilogNetlistWriter.cc.

243  {
244  stream << generateIndentation(indentationLevel, indentation) << "("
245  << endl;
246 
247  for (size_t i = 0; i < block.portCount(); i++) {
248  const NetlistPort& port = block.port(i);
249  string portName = port.name();
250  string direction = directionString(port.direction());
251  stream << generateIndentation(indentationLevel+1, indentation)
252  << direction;
253 
254  if (port.dataType() == BIT) {
255  //nothing to do
256  } else {
257  stream << "[";
258  // zero width ports as (0: 0
259  if (isNumber(port.widthFormula()) &&
260  Conversion::toInt(port.widthFormula()) == 0) {
261  stream << "0";
262  } else if (isNumber(port.widthFormula())) {
263  stream << Conversion::toInt(port.widthFormula()) - 1;
264  } else {
265  stream << port.widthFormula() << "-1";
266  }
267  stream << ":0]";
268  }
269  stream << " " << portName;
270  if (i + 1 == block.portCount()) {
271  stream << ");";
272  } else {
273  stream << ",";
274  }
275  stream << endl;
276  }
277 }

References ProGe::BIT, ProGe::NetlistPort::dataType(), ProGe::NetlistPort::direction(), directionString(), generateIndentation(), indentation(), isNumber(), ProGe::NetlistPort::name(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), Conversion::toInt(), and ProGe::NetlistPort::widthFormula().

Referenced by writeBlock().

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◆ writePortMappings()

void ProGe::VerilogNetlistWriter::writePortMappings ( const BaseNetlistBlock &  block,
std::ofstream &  stream 
) const
private

Writes the port mappings of the given block to the given stream.

Parameters
blockThe netlist block.
streamThe stream to write.

Definition at line 488 of file VerilogNetlistWriter.cc.

489  {
490  for (size_t i = 0; i < block.subBlockCount(); i++) {
491  const BaseNetlistBlock& component = block.subBlock(i);
492 
493  // virtual NetlistBlocks are omitted
494  if (component.isVirtual()) {
495  continue;
496  }
497 
498  stream << indentation(1) << component.moduleName()<< endl;
499 
500  // create generic map(parameters)
501  if (component.parameterCount() > 0) {
502  stream << indentation(1) << "#(" << endl;
503  for (size_t i = 0; i < component.parameterCount(); i++) {
504  Parameter param = component.parameter(i);
505  stream << indentation(2) << "." << param.name() << "(";
506 
507  if (param.type().lower() == PARAM_STRING) {
508  stream << genericMapStringValue(param.value());
509  } else {
510  stream << param.value();
511  }
512  if (i == component.parameterCount() - 1) {
513  stream << ")";
514  } else {
515  stream << "),";
516  }
517  stream << endl;
518  }
519  stream << indentation(1) << ")" << endl;
520  }
521  // create port map on unique(!) instance
522  stream << indentation(1) << component.instanceName()
523  << "_" << i << endl
524  << indentation(2) << "(" << endl;
525  for (size_t i = 0; i < component.portCount(); i++) {
526  const NetlistPort& port = component.port(i);
527  size_t vertexDescriptor = block.netlist().descriptor(port);
528  std::pair<out_edge_iterator, out_edge_iterator> edges =
529  boost::out_edges(vertexDescriptor, block.netlist());
530 
531  string srcConn = port.name();
532  string dstConn = "";
533  if (edges.first != edges.second) {
534  edge_descriptor edgeDescriptor = *edges.first;
535  vertex_descriptor dstVertex =
536  boost::target(edgeDescriptor, block.netlist());
537  NetlistPort* dstPort = block.netlist()[dstVertex];
538 
539  if (&dstPort->parentBlock() == &block) {
540  if (port.dataType() != dstPort->dataType()) {
541  if (port.dataType() == BIT) {
542  assert(dstPort->dataType() == BIT_VECTOR);
543  dstConn = dstPort->name() + "[0]";
544  } else {
545  assert(dstPort->dataType() == BIT);
546  srcConn += "[0]";
547  dstConn = dstPort->name();
548  }
549  } else {
550  dstConn = dstPort->name();
551  }
552  } else {
553  dstConn = portSignalName(port);
554  }
555  } else {
556  dstConn = portSignalName(port);
557  }
558  stream << indentation(3) << "." << srcConn << "(" << dstConn << ")";
559  if (i+1 < component.portCount()) {
560  stream << "," << endl;
561  }
562  }
563  stream << ");" << endl << endl;
564  }
565 }

References assert, ProGe::BIT, ProGe::BIT_VECTOR, ProGe::NetlistPort::dataType(), ProGe::Netlist::descriptor(), genericMapStringValue(), indentation(), ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::isVirtual(), TCEString::lower(), ProGe::BaseNetlistBlock::moduleName(), ProGe::Parameter::name(), ProGe::NetlistPort::name(), ProGe::BaseNetlistBlock::netlist(), PARAM_STRING, ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), ProGe::Parameter::type(), and ProGe::Parameter::value().

Referenced by writeBlock().

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◆ writeSignalAssignments()

void ProGe::VerilogNetlistWriter::writeSignalAssignments ( const BaseNetlistBlock &  block,
std::ofstream &  stream 
) const
private

Writes the signal assignments of the given block to the given stream.

Parameters
blockThe netlist block.
streamThe stream.

Definition at line 350 of file VerilogNetlistWriter.cc.

351  {
352  set<const BaseNetlistBlock*, NetlistBlockNameComparator> subBlocks;
353  for (size_t i = 0; i < block.subBlockCount(); i++) {
354  subBlocks.insert(&block.subBlock(i));
355  }
356 
357  typedef std::vector<edge_descriptor> EdgeTable;
358  EdgeTable handledEdges;
359 
360  for (size_t i = 0; i < block.subBlockCount(); i++) {
361  const BaseNetlistBlock& subBlock = block.subBlock(i);
362  for (size_t i = 0; i < subBlock.portCount(); i++) {
363  const NetlistPort& port = subBlock.port(i);
364  size_t vertexDescriptor = block.netlist().descriptor(port);
365  std::pair<out_edge_iterator, out_edge_iterator> edges =
366  boost::out_edges(vertexDescriptor, block.netlist());
367 
368  while (edges.first != edges.second) {
369  edge_descriptor edgeDescriptor = *edges.first;
370  edges.first++;
371  if (!ContainerTools::containsValue(
372  handledEdges, edgeDescriptor)) {
373  vertex_descriptor srcVertex =
374  boost::source(edgeDescriptor, block.netlist());
375  vertex_descriptor dstVertex =
376  boost::target(edgeDescriptor, block.netlist());
377  NetlistPort* srcPort = block.netlist()[srcVertex];
378  NetlistPort* dstPort = block.netlist()[dstVertex];
379 
380  if (&dstPort->parentBlock() == &block) {
381  continue;
382  }
383 
384  assert(srcPort == &port);
385  if (AssocTools::containsKey(
386  subBlocks, &srcPort->parentBlock()) &&
387  AssocTools::containsKey(
388  subBlocks, &dstPort->parentBlock())) {
389  handledEdges.push_back(edgeDescriptor);
390  // add the opposite edge too
391  std::pair<edge_descriptor, bool> opposite =
392  boost::edge(
393  dstVertex, srcVertex, block.netlist());
394  assert(opposite.second);
395  assert(opposite.first != edgeDescriptor);
396  handledEdges.push_back(opposite.first);
397 
398  PortConnectionProperty property =
399  block.netlist()[edgeDescriptor];
400  if (property.fullyConnected()) {
401  if (srcPort->direction() == OUT) {
402  stream << indentation(1) << "assign "
403  << portSignalName(*dstPort) << " = "
404  << portSignalName(*srcPort) << ";"
405  << endl;
406  } else {
407  stream << indentation(1) << "assign "
408  << portSignalName(*srcPort) << " = "
409  << portSignalName(*dstPort) << ";"
410  << endl;
411  }
412  } else {
413  string srcPortSignal;
414  if (srcPort->dataType() == BIT) {
415  srcPortSignal = portSignalName(*srcPort);
416  } else {
417  if (dstPort->dataType() == BIT) {
418  srcPortSignal =
419  portSignalName(*srcPort) + "[" +
420  Conversion::toString(
421  property.port1FirstBit()) +
422  "]";
423  } else {
424  srcPortSignal =
425  portSignalName(*srcPort) + "[" +
426  Conversion::toString(
427  property.port1FirstBit() +
428  property.width() - 1) +
429  ":" +
430  Conversion::toString(
431  property.port1FirstBit()) +
432  "]";
433  }
434  }
435  string dstPortSignal;
436  if (dstPort->dataType() == BIT) {
437  dstPortSignal = portSignalName(*dstPort);
438  } else {
439  if (srcPort->dataType() == BIT) {
440  dstPortSignal =
441  portSignalName(*dstPort) + "[" +
442  Conversion::toString(
443  property.port2FirstBit()) +
444  "]";
445  } else {
446  dstPortSignal =
447  portSignalName(*dstPort) + "[" +
448  Conversion::toString(
449  property.port2FirstBit() +
450  property.width() - 1) +
451  ":" +
452  Conversion::toString(
453  property.port2FirstBit()) +
454  "]";
455  }
456  }
457 
458  if (srcPort->direction() == OUT) {
459  stream << indentation(1) << "assign "
460  << dstPortSignal << " = "
461  << srcPortSignal << ";" << endl;
462  } else {
463  stream << indentation(1) << "assign "
464  << srcPortSignal << " = "
465  << dstPortSignal << ";" << endl;
466  }
467  }
468  }
469  }
470  }
471  }
472  }
473 
474  if (groundWidth_ > 0) {
475  stream << indentation(1) << "assign "
476  << GROUND_SIGNAL << " = {" << groundWidth_ <<"{1'b0}};"
477  << endl;
478  }
479 }

References assert, ProGe::BIT, AssocTools::containsKey(), ContainerTools::containsValue(), ProGe::NetlistPort::dataType(), ProGe::Netlist::descriptor(), ProGe::NetlistPort::direction(), GROUND_SIGNAL, groundWidth_, indentation(), ProGe::BaseNetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), and Conversion::toString().

Referenced by writeBlock().

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◆ writeSignalDeclarations()

void ProGe::VerilogNetlistWriter::writeSignalDeclarations ( const BaseNetlistBlock &  block,
std::ofstream &  stream 
)
private

Writes the Verilog signal declarations to the given stream.

Parameters
blockThe block of which the signals are written.
streamThe stream to write.

Definition at line 286 of file VerilogNetlistWriter.cc.

287  {
288  // collect all the sub blocks to a set
289  typedef std::set<const BaseNetlistBlock*, NetlistBlockNameComparator>
290  BlockSet;
291  BlockSet subBlocks;
292  for (size_t i = 0; i < block.subBlockCount(); i++) {
293  // ports belonging to virtual blocks have static values, thus they are
294  // excluded
295  if (!block.subBlock(i).isVirtual()) {
296  subBlocks.insert(&block.subBlock(i));
297  }
298  }
299 
300  // create a signal for each port in the sub-blocks
301  for (BlockSet::const_iterator iter = subBlocks.begin();
302  iter != subBlocks.end(); iter++) {
303  const BaseNetlistBlock* subBlock = *iter;
304 
305  for (size_t i = 0; i < subBlock->portCount(); i++) {
306  const NetlistPort& port = subBlock->port(i);
307 
308  size_t vertexDescriptor = block.netlist().descriptor(port);
309  std::pair<out_edge_iterator, out_edge_iterator> edges =
310  boost::out_edges(vertexDescriptor, block.netlist());
311 
312  if (edges.first != edges.second) {
313  edge_descriptor edgeDescriptor = *edges.first;
314  vertex_descriptor dstVertex =
315  boost::target(edgeDescriptor, block.netlist());
316  NetlistPort* dstPort = block.netlist()[dstVertex];
317  if (&dstPort->parentBlock() != &block) {
318  stream << indentation(1) << "wire"
319  << portSignalType(port) << " "
320  << portSignalName(port) << ";" << endl;
321  }
322  } else if (!port.hasStaticValue()) {
323  // assume the port is connected to ground if is is
324  // unconnected in the netlist
325  if (port.realWidthAvailable()) {
326  groundWidth_ =
327  std::max(port.realWidth(), groundWidth_);
328  }
329  stream << indentation(1) << "wire"
330  << portSignalType(port) << " "
331  << portSignalName(port) << ";" << endl;
332  }
333  }
334  }
335 
336  // create a ground signal
337  if (groundWidth_ > 0) {
338  stream << indentation(1) << "wire[" << groundWidth_ - 1 << ":0]"
339  << GROUND_SIGNAL << ";" << endl;
340  }
341 }

References ProGe::Netlist::descriptor(), GROUND_SIGNAL, groundWidth_, ProGe::NetlistPort::hasStaticValue(), indentation(), ProGe::BaseNetlistBlock::isVirtual(), ProGe::BaseNetlistBlock::netlist(), ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), portSignalType(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::realWidthAvailable(), ProGe::BaseNetlistBlock::subBlock(), and ProGe::BaseNetlistBlock::subBlockCount().

Referenced by writeBlock().

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Member Data Documentation

◆ groundWidth_

int ProGe::VerilogNetlistWriter::groundWidth_
private

Width of the ground signal.

Definition at line 117 of file VerilogNetlistWriter.hh.

Referenced by writeSignalAssignments(), and writeSignalDeclarations().

The documentation for this class was generated from the following files:
ProGe::VerilogNetlistWriter::generateIndentation
static std::string generateIndentation(unsigned int level, const std::string &indentation)
Definition: VerilogNetlistWriter.cc:623
ProGe::VerilogNetlistWriter::directionString
static std::string directionString(Direction direction)
Definition: VerilogNetlistWriter.cc:573
PARAM_STRING
const std::string PARAM_STRING
Definition: VerilogNetlistWriter.cc:59
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
ProGe::VerilogNetlistWriter::writeSignalDeclarations
void writeSignalDeclarations(const BaseNetlistBlock &block, std::ofstream &stream)
Definition: VerilogNetlistWriter.cc:286
AssocTools::containsKey
static bool containsKey(const ContainerType &aContainer, const KeyType &aKey)
ProGe::BIDIR
@ BIDIR
Bidirectional port.
Definition: ProGeTypes.hh:55
StringTools::indent
static std::string indent(int level)
Definition: StringTools.cc:319
ProGe::StaticSignal::VCC
@ VCC
All port signals set to high.
Definition: NetlistPort.hh:51
GROUND_SIGNAL
const std::string GROUND_SIGNAL
Definition: VerilogNetlistWriter.cc:58
ProGe::VerilogNetlistWriter::writeBlock
void writeBlock(const BaseNetlistBlock &block, const std::string &dstDirectory)
Definition: VerilogNetlistWriter.cc:139
ProGe::VerilogNetlistWriter::writePortDeclaration
static void writePortDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
Definition: VerilogNetlistWriter.cc:241
ProGe::BaseNetlistBlock::netlist
virtual const Netlist & netlist() const
Definition: BaseNetlistBlock.cc:348
Conversion::toString
static std::string toString(const T &source)
FileSystem::fileIsCreatable
static bool fileIsCreatable(const std::string fileName)
Definition: FileSystem.cc:123
ProGe::VerilogNetlistWriter::writePortMappings
void writePortMappings(const BaseNetlistBlock &block, std::ofstream &stream) const
Definition: VerilogNetlistWriter.cc:488
assert
#define assert(condition)
Definition: Application.hh:86
ProGe::Netlist::parameterCount
size_t parameterCount() const
Definition: Netlist.cc:422
InvalidData
Definition: Exception.hh:149
FileSystem::fileIsWritable
static bool fileIsWritable(const std::string fileName)
ProGe::VerilogNetlistWriter::writeNetlistParameterPackage
void writeNetlistParameterPackage(const std::string &dstDirectory) const
Definition: VerilogNetlistWriter.cc:104
ProGe::Parameter::name
const TCEString & name() const
Definition: Parameter.cc:133
__func__
#define __func__
Definition: Application.hh:67
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
ProGe::VerilogNetlistWriter::vertex_descriptor
boost::graph_traits< Netlist >::vertex_descriptor vertex_descriptor
Definition: VerilogNetlistWriter.hh:72
ProGe::VerilogNetlistWriter::edge_descriptor
boost::graph_traits< Netlist >::edge_descriptor edge_descriptor
Definition: VerilogNetlistWriter.hh:74
ProGe::VerilogNetlistWriter::netlistParameterPkgName
std::string netlistParameterPkgName() const
Definition: VerilogNetlistWriter.cc:126
FileSystem::DIRECTORY_SEPARATOR
static const std::string DIRECTORY_SEPARATOR
Definition: FileSystem.hh:189
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
ProGe::VerilogNetlistWriter::groundWidth_
int groundWidth_
Width of the ground signal.
Definition: VerilogNetlistWriter.hh:117
ProGe::VerilogNetlistWriter::portSignalType
static std::string portSignalType(const NetlistPort &port)
Definition: VerilogNetlistWriter.cc:659
ProGe::VerilogNetlistWriter::isNumber
static bool isNumber(const std::string &formula)
Definition: VerilogNetlistWriter.cc:594
ProGe::NetlistWriter::targetNetlistBlock
const BaseNetlistBlock & targetNetlistBlock() const
Definition: NetlistWriter.cc:64
ProGe::VerilogNetlistWriter::portSignalName
static std::string portSignalName(const NetlistPort &port)
Definition: VerilogNetlistWriter.cc:641
FileSystem::fileExists
static bool fileExists(const std::string fileName)
ProGe::NetlistWriter::NetlistWriter
NetlistWriter(const BaseNetlistBlock &targetBlock)
Definition: NetlistWriter.cc:46
TCEString
Definition: TCEString.hh:53
ProGe::Netlist::parameter
Parameter parameter(size_t index) const
Definition: Netlist.cc:434
ProGe::VerilogNetlistWriter::writeSignalAssignments
void writeSignalAssignments(const BaseNetlistBlock &block, std::ofstream &stream) const
Definition: VerilogNetlistWriter.cc:350
ProGe::BaseNetlistBlock::moduleName
const std::string & moduleName() const
Definition: BaseNetlistBlock.cc:140
ContainerTools::containsValue
static bool containsValue(const ContainerType &aContainer, const ElementType &aKey)
Conversion::toInt
static int toInt(const T &source)
IOException
Definition: Exception.hh:130
ProGe::VerilogNetlistWriter::genericMapStringValue
TCEString genericMapStringValue(const TCEString &generic) const
Definition: VerilogNetlistWriter.cc:676
ProGe::VerilogNetlistWriter::indentation
std::string indentation(unsigned int level) const
Definition: VerilogNetlistWriter.cc:611
ProGe::VerilogNetlistWriter::writeGenericDeclaration
static void writeGenericDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
Definition: VerilogNetlistWriter.cc:203
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
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