OpenASIP  2.0
AlmaIFIntegrator.cc
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1 /*
2  Copyright (c) 2002-2016 Tampere University.
3 
4  This file is part of TTA-Based Codesign Environment (TCE).
5 
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24 /**
25  * @file AlmaIFIntegrator.cc
26  *
27  * Implementation of AlmaIFIntegrator class.
28  */
29 
30 #include "AlmaIFIntegrator.hh"
31 #include "VhdlRomGenerator.hh"
33 #include "Machine.hh"
34 #include "HWOperation.hh"
35 #include "NetlistPort.hh"
36 #include "NetlistPortGroup.hh"
37 #include "SignalGroup.hh"
38 #include "NetlistBlock.hh"
39 #include "MachineImplementation.hh"
41 #include "DummyMemGenerator.hh"
42 #include "Conversion.hh"
43 #include "Environment.hh"
44 #include "FileSystem.hh"
45 #include "MathTools.hh"
47 
49 using ProGe::NetlistPort;
51 
55 const TCEString AlmaIFIntegrator::ALMAIF_MODULE = "tta_accel";
56 const TCEString AlmaIFIntegrator::DEFAULT_DEVICE = "xc7z020clg400-1";
57 
60 
62 }
63 
66  ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName,
67  TCEString outputDir, TCEString programName, int targetClockFreq,
68  std::ostream& warningStream, std::ostream& errorStream,
69  const MemInfo& imem, MemType dmemType, bool syncReset)
71  machine, idf, hdl, progeOutputDir, coreEntityName, outputDir,
72  programName, targetClockFreq, warningStream, errorStream, imem,
73  dmemType),
74  imemGen_(NULL),
75  dmemGen_(),
76  almaifBlock_(NULL),
77  deviceFamily_(""),
78  fileGen_(new DefaultProjectFileGenerator(coreEntityName, this)),
79  secondDmem_(false),
80  secondPmem_(false),
81  dmemHandled_(false),
82  pmemHandled_(false),
83  syncReset_(syncReset),
84  broadcast_pmem_(false) {
85  if (idf->icDecoderParameterValue("debugger") == "external") {
86  hasMinimalDebugger_ = false;
87  } else if (idf->icDecoderParameterValue("debugger") == "minimal") {
88  hasMinimalDebugger_ = true;
89  } else {
90  TCEString msg =
91  "AlmaIF interface requires connections to an external debugger.";
92  throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
93  }
94 }
95 
97 
98  if (imemGen_ != NULL) {
99  delete imemGen_;
100  }
101  if (!dmemGen_.empty()) {
102  std::map<TCEString, MemoryGenerator*>::iterator iter =
103  dmemGen_.begin();
104  while (iter != dmemGen_.end()) {
105  delete iter->second;
106  iter++;
107  }
108  }
109 }
110 
111 void
113  dmemInfo_ = pmemInfo_ = {UNKNOWN, 0, 0, 0, 0, false, "", ""};
114 
115  bool foundDmem = false;
116  bool foundPmem = false;
117 
118  // This is more or less a duplicate of parseDataMemories in the superclass
119  // to get around it not parsing memories if dmem type is 'none' and it not
120  // handling multiple lsus well
121 
122  MemInfo secondDmemInfo;
123  MemInfo secondPmemInfo;
125  this->machine()->functionUnitNavigator();
126  for (int i = 0; i < fuNav.count(); i++) {
127  TTAMachine::FunctionUnit* fu = fuNav.item(i);
128  if (fu->hasAddressSpace()) {
130  bool isLSU = false;
131  for (int i = 0; i < fu->operationCount(); ++i) {
132  std::string operation = fu->operation(i)->name();
133  std::string prefix = operation.substr(0, 2);
134  if (prefix == "ld" || prefix == "st") {
135  isLSU = true;
136  break;
137  }
138  }
139 
140  if (!isLSU) {
141  continue;
142  }
143 
144  if (as->name() == DMEM_NAME) {
145  if (foundDmem) {
146  assert(!secondDmem_ && "Found third DMEM LSU");
147  secondDmem_ = true;
148  secondDmemInfo = readLsuParameters(*fu);
149  if (secondDmemInfo.portAddrw < dmemInfo_.portAddrw) {
150  // Second DMEM should have lesser or equal data
151  // width => greater or equal address width
152  // swap if this is not the case
153  secondDmemInfo = dmemInfo_;
155  }
156  secondDmemName_ = secondDmemInfo.lsuName;
157  } else {
158  foundDmem = true;
160  if (dmem_dram_) {
161  dmemInfo_.type = DRAM;
162  }
163  }
164  } else if (as->name() == PMEM_NAME) {
165  if (foundPmem) {
166  assert(!secondPmem_ && "Found third PMEM LSU");
167  secondPmem_ = true;
168  secondPmemInfo = readLsuParameters(*fu);
169  } else {
170  foundPmem = true;
172 
173  // Needed for the case when the local memory doesn't exist
174  // and needs to reserved from the buffer memory
175  if (as->hasNumericalId(0)) {
176  hasSeparateLocalMemory_ = false;
177  }
178  }
179  }
180  }
181  }
182 
183  if (secondDmem_) {
184  secondDmemName_ = secondDmemInfo.lsuName;
186  secondDmemInfo.mauWidth * secondDmemInfo.widthInMaus;
187  secondDmemAddrw_ = secondDmemInfo.portAddrw;
188  } else if (foundDmem) {
189  secondDmemDataw_ = 32;
191  }
192 
193  if (secondPmem_) {
194  secondPmemName_ = secondPmemInfo.lsuName;
196  secondPmemInfo.mauWidth * secondDmemInfo.widthInMaus;
197  secondPmemAddrw_ = secondPmemInfo.portAddrw;
198  } else if (foundPmem) {
199  secondPmemDataw_ = 32;
201  }
202 }
203 
204 void
206  const ProGe::NetlistBlock* progeBlockInOldNetlist) {
207 
208  initPlatformNetlist(progeBlockInOldNetlist);
209  findMemories();
210  initAlmaifBlock();
211  const NetlistBlock& cores = progeBlock();
212  int coreCount = 1;
213  for (int i = 0; i < coreCount; i++) {
214  int coreId = coreCount == 1 ? -1 : i;
215  if (!integrateCore(cores, coreId)) {
216  return;
217  }
218  }
219 
221 
222  addAlmaifFiles();
223  addProGeFiles();
224 
226 }
227 
228 /**
229  * Returns the AXI bus facing address width: 2 bits for address space select
230  * + maximum of the four address space widths (byte-addressed):
231  *
232  * - CTRL block (fixed 1024 bytes per core)
233  * - Instruction memory
234  * - Data and parameter memories
235  */
236 TCEString
238  // IMEM address width
239  int imemAddressWidth = 0;
240  if (imemInfo().type != VHDL_ARRAY) {
241  imemAddressWidth =
243  (imemInfo().widthInMaus * imemInfo().mauWidth + 7) / 8 - 1) +
245  }
246  // Debugger address space:
247  int debugAddressWidth = 8;
248  int dmemAddressWidth =
251  std::max(0, dmemInfo_.mauWidth * dmemInfo_.widthInMaus / 8 - 1));
252 
253  // Skip param if its width is set by a generic: if there is a larger
254  // memory (imem/dmem), the value will still be correct
255  int pmemAddressWidth = 0;
256  if (pmemInfo_.asAddrw != 32) {
257  pmemAddressWidth =
260  0, pmemInfo_.mauWidth * pmemInfo_.widthInMaus / 8 - 1));
261  } else {
262  pmemAddressWidth = DEFAULT_LOCAL_MEMORY_WIDTH;
263  }
264  int axiAddressWidth = std::max(
265  std::max(imemAddressWidth, debugAddressWidth),
266  std::max(dmemAddressWidth, pmemAddressWidth));
267 
269 }
270 
271 void
273  ProGe::Netlist& netlist = integratorBlock()->netlist();
274  TCEString core_count = "1";
275 
276  TCEString platformPath = Environment::dataDirPath("ProGe");
277  platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
279 
280  int imemdataw = imemInfo().mauWidth * imemInfo().widthInMaus;
281  int imemaddrw = imemInfo().portAddrw;
282  int imemAxiAddrw =
283  MathTools::requiredBits0Bit0((imemdataw + 31) / 32 - 1) + imemaddrw;
284  int bustrace_width = 0;
285 
286  if (imem_dp_) {
287  imemdataw = MathTools::roundUpToPowerTwo(imemdataw);
288  }
289 
290  for (int i = 0; i < machine()->busNavigator().count(); ++i) {
291  int bus_width = machine()->busNavigator().item(i)->width();
292  // Busess are padded to a multiple of 32 bits
293  bus_width = (bus_width + 31) / 32 * 32;
294  bustrace_width += bus_width;
295  }
296 
300  "axi_addr_width_g", "integer", axiAddressWidth());
301  integratorBlock()->setParameter("axi_id_width_g", "integer", "12");
302  almaifBlock_->setParameter("core_count_g", "integer", core_count);
304  "axi_addr_width_g", "integer", "axi_addr_width_g");
305  almaifBlock_->setParameter("axi_id_width_g", "integer", "axi_id_width_g");
306 
308  "imem_addr_width_g", "integer", Conversion::toString(imemaddrw));
309 
311  "imem_axi_addr_width_g", "integer",
312  Conversion::toString(imemAxiAddrw));
313  if (imemInfo().type != VHDL_ARRAY) {
315  "imem_data_width_g", "integer", Conversion::toString(imemdataw));
316  } else {
317  almaifBlock_->setParameter("imem_data_width_g", "integer", "0");
318  }
319 
321  "bus_count_g", "integer", Conversion::toString(bustrace_width / 32));
323  "local_mem_addrw_g", "integer", "local_mem_addrw_g");
324 
325  // Add and connect clock and reset ports
326  NetlistPort* clk =
327  new NetlistPort("clk", "1", 1, ProGe::BIT, ProGe::IN, *almaifBlock_);
328  NetlistPort* rstx =
329  new NetlistPort("rstx", "1", 1, ProGe::BIT, ProGe::IN, *almaifBlock_);
330  netlist.connect(*clockPort(), *clk);
331  netlist.connect(*resetPort(), *rstx);
332 
334  "second_dmem_data_width_g", "integer",
337  "second_dmem_addr_width_g", "integer",
339 
340  if (secondDmem_) {
341  almaifBlock_->setParameter("enable_second_dmem_g", "integer", "1");
343  "second-dmem-port-declarations",
344  Path(platformPath + "second_dmem_port_declaration.snippet"));
345  } else {
346  almaifBlock_->setParameter("enable_second_dmem_g", "integer", "0");
348  "second-dmem-signal-declarations",
349  Path(platformPath + "second_dmem_signal_declaration.snippet"));
350  }
351 
352  if (secondPmem_) {
353  almaifBlock_->setParameter("enable_second_pmem_g", "integer", "1");
355  "second-pmem-port-declarations",
356  Path(platformPath + "second_pmem_port_declaration.snippet"));
357  } else {
358  almaifBlock_->setParameter("enable_second_pmem_g", "integer", "0");
360  "second-pmem-signal-declarations",
361  Path(platformPath + "second_pmem_signal_declaration.snippet"));
362  }
363 
365  "second_pmem_data_width_g", "integer",
367  if (pmemInfo_.asAddrw == 32) {
369  "second_pmem_addr_width_g", "integer", "local_mem_addrw_g");
370  } else {
372  "second_pmem_addr_width_g", "integer",
374  }
375 
376  if (syncReset_) {
377  almaifBlock_->setParameter("sync_reset_g", "integer", "1");
378  } else {
379  almaifBlock_->setParameter("sync_reset_g", "integer", "0");
380  }
381 
382  if (broadcast_pmem_) {
383  almaifBlock_->setParameter("broadcast_pmem_g", "integer", "1");
384 
386  "pmem-bcast", Path(platformPath + "pmem_broadcast.snippet"));
387  } else {
388  almaifBlock_->setParameter("broadcast_pmem_g", "integer", "0");
389  }
390 
391  // Add AXI4 slave interface to AlmaIF block and toplevel, and connect them
392  NetlistPortGroup* axislave_almaif = axiSlavePortGroup();
393  NetlistPortGroup* axislave_ext = axislave_almaif->clone();
394  almaifBlock_->addPortGroup(axislave_almaif);
395  integratorBlock()->addPortGroup(axislave_ext);
396  netlist.connectGroupByName(*axislave_almaif, *axislave_ext);
397 
398  if (pmemInfo_.asAddrw == 32) {
399  assert(
400  broadcast_pmem_ == false &&
401  "Broadcasting pmem not supported with m_axi");
403  "local_mem_addrw_g", "integer",
405 
407  "axi_offset_low_g", "integer", "1136656384");
408  integratorBlock()->setParameter("axi_offset_high_g", "integer", "0");
410  "axi_offset_low_g", "integer", "axi_offset_low_g");
412  "axi_offset_high_g", "integer", "axi_offset_high_g");
413 
414  NetlistPortGroup* aximaster_almaif = axiMasterPortGroup();
415  NetlistPortGroup* aximaster_ext = aximaster_almaif->clone();
416  almaifBlock_->addPortGroup(aximaster_almaif);
417  integratorBlock()->addPortGroup(aximaster_ext);
418  netlist.connectGroupByName(*aximaster_almaif, *aximaster_ext);
419  } else {
421  "local_mem_addrw_g", "integer",
423  almaifBlock_->setParameter("axi_offset_low_g", "integer", "0");
425  "axi_offset_high_g", "integer", "0");
426  }
427 
428  int coreCount = 1;
429  // Debug signals
430  if (!hasMinimalDebugger_) {
431  almaifBlock_->setParameter("full_debugger_g", "integer", "1");
433  "full-debugger-port-declarations",
434  Path(platformPath + "full_debugger_port_declaration.snippet"));
436  "debugger", Path(platformPath + "full_debugger.snippet"));
437 
439  "core_db_pc_start", coreCount * imemaddrw, ProGe::OUT,
440  "db_pc_start");
442  "core_db_pc_next", coreCount * imemaddrw, ProGe::IN,
443  "db_pc_next");
445  "core_db_bustraces", coreCount * bustrace_width, ProGe::IN,
446  "db_bustraces");
447  } else {
448  almaifBlock_->setParameter("full_debugger_g", "integer", "0");
450  "mini-debugger-signal-declarations",
451  Path(platformPath + "mini_debugger_signal_declaration.snippet"));
453  "debugger", Path(platformPath + "mini_debugger.snippet"));
454  }
455 
456  // Set the default value in case when there is no separate scratchpad memory.
457  // AlmaIF interface must reserve some part of the global buffer memory
458  // (pmem) and communicate that in the interface
461  "reserved_sp_bytes_g", "integer",
463  }
464 
466  "core_db_pc", coreCount * imemaddrw, ProGe::IN, "db_pc");
468  "core_db_lockcnt", coreCount * 64, ProGe::IN, "db_lockcnt");
470  "core_db_cyclecnt", coreCount * 64, ProGe::IN, "db_cyclecnt");
472  "core_db_tta_nreset", coreCount, ProGe::OUT, "db_tta_nreset");
474  "core_db_lockrq", coreCount, ProGe::OUT, "db_lockrq");
475  if (dmem_dram_) {
477  "core_db_dram_offset", 32, ProGe::OUT, "db_dram_offset");
479  "dram-offset-port-declaration",
480  "core_db_dram_offset : out std_logic_vector(32-1 downto 0);");
481  // We want to disable dmem from tta-accel, because dmem exists in dram
483  "enable-dmem", "constant enable_dmem : boolean := false;");
484  } else {
485  // Dummy signal to connect to not leave minidebuggers portmap
486  // undefined
488  "dram-offset-dummy-declaration",
489  "signal core_db_dram_offset : std_logic_vector(32-1 downto 0);");
491  "enable-dmem",
492  "constant enable_dmem : boolean := dmem_data_width_g > 0;");
493  }
494 
495  if (imemInfo().type != VHDL_ARRAY) {
496  // Ifetch signals
497  addPortToAlmaIFBlock("core_busy_out", coreCount, ProGe::OUT, "busy");
499  "core_imem_data_out", coreCount * imemdataw, ProGe::OUT,
500  "imem_data");
502  "core_imem_en_x_in", coreCount, ProGe::IN, "imem_en_x");
504  "core_imem_addr_in", coreCount * imemaddrw, ProGe::IN,
505  "imem_addr");
506 
507  if (imem_dp_) {
508  const int strb_width = imemdataw / 8;
509  const int half_cores_ceil = (coreCount + 1) / 2;
510  // Dualport memories have identical a-b ports, except with odd
511  // corecounts the b is full and the a's msb-side is unconnected
513  "INSTR_a", half_cores_ceil, imemdataw * half_cores_ceil,
514  imemaddrw * half_cores_ceil, strb_width * half_cores_ceil,
515  false);
517  "INSTR_b", half_cores_ceil, imemdataw * half_cores_ceil,
518  imemaddrw * half_cores_ceil, strb_width * half_cores_ceil,
519  false);
520  } else {
521  addMemoryPorts("INSTR_a", imemdataw, imemaddrw, false, false);
522  addMemoryPorts("INSTR_b", 32, imemAxiAddrw, false, false);
523  }
524  TCEString platformPath = Environment::dataDirPath("ProGe");
525  platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
527 
529  "imem-statements",
530  Path(platformPath + "imem_statements.snippet"));
531  if (imem_dp_) {
533  "imem-bcast",
534  Path(platformPath + "imem_broadcast_dualport.snippet"));
536  "imem-port-declarations",
537  Path(
538  platformPath + "imem_port_declaration_dualport.snippet"));
539  } else {
541  "imem-bcast", Path(platformPath + "imem_broadcast.snippet"));
543  "imem-port-declarations",
544  Path(platformPath + "imem_port_declaration.snippet"));
545  }
546  }
547 
548  connectCoreMemories(dmemInfo_, "dmem", "data", secondDmem_);
549  connectCoreMemories(pmemInfo_, "pmem", "param", secondPmem_);
550 }
551 
552 void
554  MemInfo mem, TCEString mem_name, TCEString mem_block_name, bool seconds) {
556  mem_name + "_data_width_g", "integer",
559  mem_name + "_addr_width_g", "integer",
561 
562  TCEString platformPath = Environment::dataDirPath("ProGe");
563  platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
565 
566  // If given memory wasn't found by findMemories(), we need dummy signals
567  // as a stand-in for the missing ports
568  if (mem.portAddrw == 0 || mem.type == DRAM) {
569  Path snippet(platformPath + mem_name + "_signal_declaration.snippet");
571  mem_name + "-signal-declarations", snippet);
572  return;
573  }
574 
575  // Otherwise, instantiate the ports
576  if (mem_name == "pmem" && broadcast_pmem_) {
577  Path snippet(platformPath + "pmem_port_declaration_wide.snippet");
579  mem_name + "-port-declarations", snippet);
580  } else {
581  Path snippet(platformPath + mem_name + "_port_declaration.snippet");
583  mem_name + "-port-declarations", snippet);
584  }
585 
586  TCEString lsu_prefix = "fu_" + mem.lsuName;
587 
588  int coreCount = 1;
590  "core_" + mem_name + "_avalid_in", coreCount, ProGe::IN,
591  lsu_prefix + "_avalid_out");
593  "core_" + mem_name + "_aready_out", coreCount, ProGe::OUT,
594  lsu_prefix + "_aready_in");
596  "core_" + mem_name + "_aaddr_in", coreCount * mem.portAddrw,
597  ProGe::IN, lsu_prefix + "_aaddr_out");
599  "core_" + mem_name + "_awren_in", coreCount, ProGe::IN,
600  lsu_prefix + "_awren_out");
602  "core_" + mem_name + "_astrb_in",
603  (mem.mauWidth * mem.widthInMaus + 7) / 8 * coreCount, ProGe::IN,
604  lsu_prefix + "_astrb_out");
605 
607  "core_" + mem_name + "_adata_in",
608  coreCount * mem.mauWidth * mem.widthInMaus, ProGe::IN,
609  lsu_prefix + "_adata_out");
611  "core_" + mem_name + "_rvalid_out", coreCount, ProGe::OUT,
612  lsu_prefix + "_rvalid_in");
614  "core_" + mem_name + "_rready_in", coreCount, ProGe::IN,
615  lsu_prefix + "_rready_out");
617  "core_" + mem_name + "_rdata_out",
618  coreCount * mem.mauWidth * mem.widthInMaus, ProGe::OUT,
619  lsu_prefix + "_rdata_in");
620 
621  if (seconds) {
622  int addrWidth, dataWidth;
623  if (mem.asName == DMEM_NAME) {
624  addrWidth = secondDmemAddrw_;
625  dataWidth = secondDmemDataw_;
626  lsu_prefix = "fu_" + secondDmemName_;
627  } else {
628  addrWidth = secondPmemAddrw_;
629  dataWidth = secondPmemDataw_;
630  lsu_prefix = "fu_" + secondPmemName_;
631  }
633  "core_" + mem_name + "_2nd_avalid_in", coreCount, ProGe::IN,
634  lsu_prefix + "_avalid_out");
636  "core_" + mem_name + "_2nd_aready_out", coreCount, ProGe::OUT,
637  lsu_prefix + "_aready_in");
639  "core_" + mem_name + "_2nd_aaddr_in", coreCount * addrWidth,
640  ProGe::IN, lsu_prefix + "_aaddr_out");
642  "core_" + mem_name + "_2nd_awren_in", coreCount, ProGe::IN,
643  lsu_prefix + "_awren_out");
645  "core_" + mem_name + "_2nd_astrb_in", coreCount * dataWidth / 8,
646  ProGe::IN, lsu_prefix + "_astrb_out");
647 
649  "core_" + mem_name + "_2nd_adata_in", coreCount * dataWidth,
650  ProGe::IN, lsu_prefix + "_adata_out");
652  "core_" + mem_name + "_2nd_rvalid_out", coreCount, ProGe::OUT,
653  lsu_prefix + "_rvalid_in");
655  "core_" + mem_name + "_2nd_rready_in", coreCount, ProGe::IN,
656  lsu_prefix + "_rready_out");
658  "core_" + mem_name + "_2nd_rdata_out", coreCount * dataWidth,
659  ProGe::OUT, lsu_prefix + "_rdata_in");
660  }
661 
663  mem_block_name + "_a", mem.mauWidth * mem.widthInMaus, mem.portAddrw,
664  mem.isShared, (mem.asAddrw == 32 && (mem.asName == PMEM_NAME)));
665  if (mem.asName == DMEM_NAME) {
667  mem_block_name + "_b", secondDmemDataw_, secondDmemAddrw_,
668  mem.isShared, false);
669  } else {
670  bool make_local_sized =
671  mem.asAddrw == 32 && (mem.asName == PMEM_NAME);
673  mem_block_name + "_b", secondPmemDataw_, secondPmemAddrw_,
674  mem.isShared, make_local_sized);
675  }
676 }
677 
678 void
680  const TCEString name, const TCEString width, const ProGe::Direction dir,
681  const TCEString core_name) {
682  NetlistPort* port =
683  new NetlistPort(name, width, ProGe::BIT_VECTOR, dir, *almaifBlock_);
684  if (core_name != "") almaif_ttacore_ports[core_name] = port;
685 }
686 
687 void
689  const TCEString name, const int width, const ProGe::Direction dir,
690  const TCEString core_name) {
691  NetlistPort* port = new NetlistPort(
692  name, Conversion::toString(width), width, ProGe::BIT_VECTOR, dir,
693  *almaifBlock_);
694  if (core_name != "") almaif_ttacore_ports[core_name] = port;
695 }
696 
697 void
699  NetlistPortGroup* port_group, const ProGe::Direction dir,
700  const TCEString name, const TCEString width) {
702  if (width == "1") {
703  type = ProGe::BIT;
704  }
705  NetlistPort* port = new NetlistPort(name, width, type, dir);
706  port_group->addPort(*port);
707 }
708 
709 /**
710  * Builds a representation of the AXI4 bus slave interface as a port group.
711  * Hardcoded signal widths for data (32b) and IDs (12b)
712  */
716 
717  addPortToGroup(axiBus, ProGe::IN, "s_axi_awid", "axi_id_width_g");
718  addPortToGroup(axiBus, ProGe::IN, "s_axi_awaddr", "axi_addr_width_g");
719  addPortToGroup(axiBus, ProGe::IN, "s_axi_awlen", "8");
720  addPortToGroup(axiBus, ProGe::IN, "s_axi_awsize", "3");
721  addPortToGroup(axiBus, ProGe::IN, "s_axi_awburst", "2");
722  addPortToGroup(axiBus, ProGe::IN, "s_axi_awvalid", "1");
723  addPortToGroup(axiBus, ProGe::OUT, "s_axi_awready", "1");
724  addPortToGroup(axiBus, ProGe::IN, "s_axi_wdata", "32");
725  addPortToGroup(axiBus, ProGe::IN, "s_axi_wstrb", "4");
726  addPortToGroup(axiBus, ProGe::IN, "s_axi_wvalid", "1");
727  addPortToGroup(axiBus, ProGe::OUT, "s_axi_wready", "1");
728  addPortToGroup(axiBus, ProGe::OUT, "s_axi_bid", "axi_id_width_g");
729  addPortToGroup(axiBus, ProGe::OUT, "s_axi_bresp", "2");
730  addPortToGroup(axiBus, ProGe::OUT, "s_axi_bvalid", "1");
731  addPortToGroup(axiBus, ProGe::IN, "s_axi_bready", "1");
732  addPortToGroup(axiBus, ProGe::IN, "s_axi_arid", "axi_id_width_g");
733  addPortToGroup(axiBus, ProGe::IN, "s_axi_araddr", "axi_addr_width_g");
734  addPortToGroup(axiBus, ProGe::IN, "s_axi_arlen", "8");
735  addPortToGroup(axiBus, ProGe::IN, "s_axi_arsize", "3");
736  addPortToGroup(axiBus, ProGe::IN, "s_axi_arburst", "2");
737  addPortToGroup(axiBus, ProGe::IN, "s_axi_arvalid", "1");
738  addPortToGroup(axiBus, ProGe::OUT, "s_axi_arready", "1");
739  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rid", "axi_id_width_g");
740  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rdata", "32");
741  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rresp", "2");
742  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rlast", "1");
743  addPortToGroup(axiBus, ProGe::OUT, "s_axi_rvalid", "1");
744  addPortToGroup(axiBus, ProGe::IN, "s_axi_rready", "1");
745 
746  return axiBus;
747 }
748 
749 /**
750  * Builds a representation of the AXI4-Lite master interface as a port group.
751  */
755 
756  addPortToGroup(axiBus, ProGe::OUT, "m_axi_awaddr", "32");
757  addPortToGroup(axiBus, ProGe::OUT, "m_axi_awvalid", "1");
758  addPortToGroup(axiBus, ProGe::IN, "m_axi_awready", "1");
759  addPortToGroup(axiBus, ProGe::OUT, "m_axi_awprot", "3");
760  addPortToGroup(axiBus, ProGe::OUT, "m_axi_wvalid", "1");
761  addPortToGroup(axiBus, ProGe::IN, "m_axi_wready", "1");
762  addPortToGroup(axiBus, ProGe::OUT, "m_axi_wdata", "32");
763  addPortToGroup(axiBus, ProGe::OUT, "m_axi_wstrb", "4");
764  addPortToGroup(axiBus, ProGe::IN, "m_axi_bvalid", "1");
765  addPortToGroup(axiBus, ProGe::OUT, "m_axi_bready", "1");
766  addPortToGroup(axiBus, ProGe::OUT, "m_axi_arvalid", "1");
767  addPortToGroup(axiBus, ProGe::IN, "m_axi_arready", "1");
768  addPortToGroup(axiBus, ProGe::OUT, "m_axi_araddr", "32");
769  addPortToGroup(axiBus, ProGe::OUT, "m_axi_arprot", "3");
770  addPortToGroup(axiBus, ProGe::IN, "m_axi_rdata", "32");
771  addPortToGroup(axiBus, ProGe::IN, "m_axi_rvalid", "1");
772  addPortToGroup(axiBus, ProGe::OUT, "m_axi_rready", "1");
773 
774  return axiBus;
775 }
776 
777 void
779  const TCEString prefix, int data_width, int addr_width,
780  const bool /* isShared */, const bool overrideAsWidth) {
781  int mem_count = 1;
782 
783  data_width = data_width * mem_count;
784  addr_width = addr_width * mem_count;
785  // In case the data_width has been already multiplied by the mem_count,
786  // we have to undo the multiplication, so the rounding is done properly
787  // for the single memory version and only then multiplied by the
788  // mem_count.
789  int strb_width = (data_width / mem_count + 7) / 8 * mem_count;
790 
792  prefix, mem_count, data_width, addr_width, strb_width,
793  overrideAsWidth);
794 }
795 
796 void
798  const TCEString prefix, int mem_count, int data_width, int addr_width,
799  int strb_width, const bool overrideAsWidth) {
800  addPortToAlmaIFBlock(prefix + "_avalid_out", mem_count, ProGe::OUT);
801  addPortToAlmaIFBlock(prefix + "_aready_in", mem_count, ProGe::IN);
802  if (overrideAsWidth) {
804  prefix + "_aaddr_out", "local_mem_addrw_g", ProGe::OUT);
805  } else {
806  addPortToAlmaIFBlock(prefix + "_aaddr_out", addr_width, ProGe::OUT);
807  }
808  addPortToAlmaIFBlock(prefix + "_awren_out", mem_count, ProGe::OUT);
809  addPortToAlmaIFBlock(prefix + "_astrb_out", strb_width, ProGe::OUT);
810  addPortToAlmaIFBlock(prefix + "_adata_out", data_width, ProGe::OUT);
811  addPortToAlmaIFBlock(prefix + "_rvalid_in", mem_count, ProGe::IN);
812  addPortToAlmaIFBlock(prefix + "_rready_out", mem_count, ProGe::OUT);
813  addPortToAlmaIFBlock(prefix + "_rdata_in", data_width, ProGe::IN);
814 }
815 
816 void
818  const std::string DS = FileSystem::DIRECTORY_SEPARATOR;
819  std::vector<TCEString> almaifFiles;
820 
821  TCEString basePath = Environment::dataDirPath("ProGe");
822  TCEString platformPath = basePath + DS + "platform" + DS;
823  TCEString dbPath = basePath + DS + "debugger" + DS;
824 
825  TCEString outputPath = outputFilePath("tta-accel.vhdl", true);
826  if (pmemInfo_.asAddrw == 32) {
827  Path snippet(platformPath + "axi_master_port_declaration.snippet");
829  "m-axi-port-declarations", snippet);
830  } else {
831  Path snippet(platformPath + "axi_master_signal_declaration.snippet");
833  "m-axi-signal-declarations", snippet);
834  }
835 
837  platformPath + "tta-accel.vhdl.tmpl", outputPath);
838  almaifFiles.push_back(outputPath);
839 
840  copyPlatformFile(platformPath + "tta-axislave.vhdl", almaifFiles);
841  copyPlatformFile(platformPath + "almaif_decoder.vhdl", almaifFiles);
842  copyPlatformFile(platformPath + "almaif_axi_arbiter.vhdl", almaifFiles);
843  copyPlatformFile(platformPath + "almaif_mc_arbiter.vhdl", almaifFiles);
844  copyPlatformFile(platformPath + "almaif_axi_expander.vhdl", almaifFiles);
845  copyPlatformFile(platformPath + "membus_splitter.vhdl", almaifFiles);
846  copyPlatformFile(platformPath + "almaif_membus_delay.vhdl", almaifFiles);
847  copyPlatformFile(dbPath + "registers-pkg.vhdl", almaifFiles);
848 
849  if (hasMinimalDebugger_) {
850  copyPlatformFile(dbPath + "minidebugger.vhdl", almaifFiles);
851  } else {
852  copyPlatformFile(dbPath + "dbregbank.vhdl", almaifFiles);
853  copyPlatformFile(dbPath + "dbsm-entity.vhdl", almaifFiles);
854  copyPlatformFile(dbPath + "dbsm-rtl.vhdl", almaifFiles);
855  copyPlatformFile(dbPath + "debugger.vhdl", almaifFiles);
856  }
857 
858  // Copy synthesis scripts
859  TCEString scriptPath = basePath + DS + "synthesis" + DS;
862  "toplevel_entity", coreEntityName() + "_toplevel");
863  copyPlatformFile(scriptPath + "find_fmax.py", almaifFiles, true);
864  outputPath = progeFilePath("timing.tcl", true);
866  scriptPath + "timing.tcl.tmpl", outputPath);
867  outputPath = progeFilePath("utilization.tcl", true);
869  scriptPath + "utilization.tcl.tmpl", outputPath);
870 
871  for (unsigned int i = 0; i < almaifFiles.size(); i++) {
872  projectFileGenerator()->addHdlFile(almaifFiles.at(i));
873  }
874 }
875 
876 void
878  const TCEString inputPath, std::vector<TCEString>& fileList,
879  bool isScript) const {
881  if (isScript) {
882  outputPath = progeFilePath(FileSystem::fileOfPath(inputPath), true);
883  } else {
885  }
886 
887  FileSystem::copy(inputPath, outputPath);
888  fileList.push_back(outputPath);
889 }
890 
891 bool
893  ProGe::Netlist& netlist = integratorBlock()->netlist();
894 
897 
898  if (!createMemories(coreId)) {
899  return false;
900  }
901 
902  // Connect cycle count, stall count ports if needed by an FU
903  auto ttaCCPort = core.port("debug_cycle_count_in");
904  if (ttaCCPort) {
905  netlist.connect(*core.port("db_cyclecnt"), *ttaCCPort);
906  }
907  auto ttaLCPort = core.port("debug_lock_count_in");
908  if (ttaLCPort) {
909  netlist.connect(*core.port("db_lockcnt"), *ttaLCPort);
910  }
911  for (size_t i = 0; i < core.portCount(); ++i) {
912  TCEString portName = core.port(i).name();
913 
914  // Connect global clock and reset ports
915  if (portName == PlatformIntegrator::TTA_CORE_CLK) {
916  netlist.connect(*clockPort(), core.port(i));
917  } else if (portName == PlatformIntegrator::TTA_CORE_RSTX) {
918  netlist.connect(*resetPort(), core.port(i));
919  } else {
920  // Strip coreN_ -prefix for multicore TTAs
921  if (portName.substr(0, 4) == "core") {
922  TCEString coreKey;
923  coreKey << "core" << coreId;
924  size_t cutoff = portName.find_first_of('_');
925  if (portName.substr(0, cutoff) != coreKey) {
926  // Port doesn't belong to core, skip
927  continue;
928  }
929  portName = portName.substr(cutoff + 1);
930  }
931  if (almaif_ttacore_ports.find(portName) !=
932  almaif_ttacore_ports.end()) {
933  int portWidth = almaif_ttacore_ports[portName]->realWidth();
934 
935  // Connect AlmaIF block to TTA
936 
937  if (coreId != -1 && imem_dp_ && portName == "imem_data") {
938  // imem_dp_ works with padded imem data signals. So here
939  // we connect only the real bits, but with padded
940  // differences.
941  netlist.connect(
942  core.port(i), *almaif_ttacore_ports[portName], 0,
943  portWidth * coreId, imemInfo().mauWidth);
944 
945  } else if (coreId != -1) {
946  netlist.connect(
947  core.port(i), *almaif_ttacore_ports[portName], 0,
948  portWidth * coreId, portWidth);
949  } else {
950  netlist.connect(
951  core.port(i), *almaif_ttacore_ports[portName]);
952  }
953  } else if (
954  dmem_dram_ &&
955  portName ==
956  (boost::format("fu_%s_dram_offset") % dmemInfo_.lsuName)
957  .str()) {
958  netlist.connect(
959  core.port(i), *almaifBlock_->port("db_dram_offset"));
960  }
961  }
962  }
963 
964  exportUnconnectedPorts(coreId);
965  return true;
966 }
967 
968 void
971 
972  for (size_t i = 0; i < almaifBlock_->portCount(); i++) {
973  const NetlistPort& port = almaifBlock_->port(i);
974  if (!integratorBlock()->netlist().isPortConnected(port)) {
975  connectToplevelPort(port);
976  }
977  }
978 }
979 
981 AlmaIFIntegrator::imemInstance(MemInfo imem, int /* coreId */) {
982  assert(imem.type != UNKNOWN && "Imem type not set!");
983  int axiAddrWidth =
985  (imemInfo().widthInMaus * imemInfo().mauWidth + 31) / 32 - 1) +
987  if (imemGen_ == NULL) {
988  if (imem.type == ONCHIP) {
989  if (imem_dp_) {
992  imem.widthInMaus, imem.portAddrw,
994  imem.portAddrw, this, warningStream(), errorStream(),
995  true, almaifBlock_, "INSTR", false, false);
996  } else {
998  imem.mauWidth, imem.widthInMaus, imem.portAddrw, 32,
999  axiAddrWidth, this, warningStream(), errorStream(), true,
1000  almaifBlock_, "INSTR", false, false);
1001  }
1002  } else if (imem.type == VHDL_ARRAY) {
1003  imemGen_ = new VhdlRomGenerator(
1004  imem.mauWidth, imem.widthInMaus, imem.portAddrw,
1005  programName() + "_imem_pkg.vhdl", this, warningStream(),
1006  errorStream());
1007  } else if (imem.type != NONE) {
1008  TCEString msg = "Unsupported instruction memory type";
1009  throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
1010  }
1011  }
1012  return *imemGen_;
1013 }
1014 
1017  MemInfo dmem, TTAMachine::FunctionUnit& lsuArch,
1018  std::vector<std::string> lsuPorts) {
1019  if (dmem.asName ==
1020  AXI_AS_NAME) { // AXI bus, export all ports to toplevel
1021  return *(new DummyMemGenerator(
1022  dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1023  warningStream(), errorStream()));
1024  }
1025 
1026  bool genSingleRam = false;
1027  bool genDualPortRam = false;
1028  bool overrideAsWidth = false;
1029  bool isDmem = dmem.asName == DMEM_NAME;
1030  bool isPmem = dmem.asName == PMEM_NAME;
1031  bool isSecondInstance = false;
1032 
1033  if (dmem.type == DRAM) { // AXI bus, export all ports to toplevel
1034  return *(new DummyMemGenerator(
1035  dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1036  warningStream(), errorStream()));
1037  }
1038 
1039  int bDataWidth = 0;
1040  int bAddrWidth = 0;
1041 
1042  if (isDmem || isPmem) {
1043  genDualPortRam = true;
1044  genSingleRam = dmem.isShared;
1045  if (isDmem) {
1046  if (dmemHandled_) {
1047  isSecondInstance = true;
1048  }
1049  dmem = dmemInfo_;
1050  bDataWidth = secondDmemDataw_;
1051  bAddrWidth = secondDmemAddrw_;
1052  dmemHandled_ = true;
1053  }
1054  if (isPmem) {
1055  if (pmemHandled_) {
1056  isSecondInstance = true;
1057  }
1058  dmem = pmemInfo_;
1059  bDataWidth = secondPmemDataw_;
1060  bAddrWidth = secondPmemAddrw_;
1061  pmemHandled_ = true;
1062  }
1063 
1064  // TODO: Assumes 32b wide memory (32b address - 2 mask bits)
1065  // (the AXI-lite IF also assumes this)
1066  if (dmem.asName == PMEM_NAME && dmem.asAddrw == 32) {
1067  overrideAsWidth = true;
1068  }
1069  }
1070 
1071  MemoryGenerator* memGen = NULL;
1072 
1073  if ((isSecondInstance && dmem.isShared) || dmem.type == DRAM) {
1074  memGen = new DummyMemGenerator(
1075  dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1076  warningStream(), errorStream());
1077  } else if (dmemGen_.find(dmem.asName) != dmemGen_.end()) {
1078  memGen = dmemGen_.find(dmem.asName)->second;
1079  } else {
1080  if (dmem.type == ONCHIP) {
1081  // onchip mem size is scalable, use value from adf's Address Space
1082  int addrw = dmem.portAddrw;
1083  memGen = new XilinxBlockRamGenerator(
1084  dmem.mauWidth, dmem.widthInMaus, addrw, bDataWidth,
1085  bAddrWidth, this, warningStream(), errorStream(),
1086  genDualPortRam, almaifBlock_, dmem.asName, overrideAsWidth,
1087  genSingleRam);
1088  } else {
1089  TCEString msg = "Unsupported data memory type";
1090  throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
1091  }
1092  memGen->addLsu(lsuArch, lsuPorts);
1093  dmemGen_[dmem.asName] = memGen;
1094  }
1095  return *memGen;
1096 }
1097 
1098 void
1099 AlmaIFIntegrator::printInfo(std::ostream& stream) const {
1100  stream
1101  << "Integrator name: AlmaIFIntegrator" << std::endl
1102  << "-----------------------------" << std::endl
1103  << "Integrates the processor core to an AXI4 bus interface according "
1104  << "to ALMARVI HW Integration Interface specification." << std::endl
1105  << "Supported instruction memory types are 'onchip' and 'none'."
1106  << std::endl
1107  << "Supported data memory types are 'onchip' and 'none'." << std::endl
1108  << "Data and Parameter memory spaces must be named '" << DMEM_NAME
1109  << "' and '" << PMEM_NAME << "' respectively." << std::endl
1110  << std::endl;
1111 }
1112 
1113 bool
1115  return true;
1116 }
1117 
1118 TCEString
1120 
1121  return deviceFamily_;
1122 }
1123 
1124 void
1126 
1127  deviceFamily_ = devFamily;
1128 }
1129 
1130 // these are not relevant here
1131 TCEString
1133  return "";
1134 }
1135 
1136 TCEString
1138  return "";
1139 }
1140 
1141 int
1143  return 1;
1144 }
1145 
1146 TCEString
1148  return "";
1149 }
1150 
1153  return fileGen_;
1154 }
XilinxBlockRamGenerator
Definition: XilinxBlockRamGenerator.hh:41
AlmaIFIntegrator::accelInstantiator_
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Definition: AlmaIFIntegrator.hh:149
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Definition: PlatformIntegrator.cc:317
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virtual const Netlist & netlist() const
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Definition: NetlistPortGroup.cc:169
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static const int DEFAULT_LOCAL_MEMORY_WIDTH
Definition: AlmaIFIntegrator.hh:127
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Definition: FileSystem.hh:197
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static const TCEString AXI_AS_NAME
Definition: AlmaIFIntegrator.hh:122
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Definition: PlatformIntegrator.cc:692
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TCEString coreEntityName() const
Definition: PlatformIntegrator.cc:126
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TTAMachine::Machine * machine
the architecture definition of the estimated processor
Definition: EstimatorCmdLineUI.cc:59
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ProGe::NetlistPortGroup * axiMasterPortGroup()
Definition: AlmaIFIntegrator.cc:753
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Definition: AddressSpace.hh:51
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virtual TCEString deviceFamily() const
Definition: AlmaIFIntegrator.cc:1119
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std::string secondDmemName_
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@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
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Definition: MemoryGenerator.hh:67
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TCEString deviceName() const
Definition: PlatformIntegrator.hh:114
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Definition: AddressSpace.cc:383
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virtual void setDeviceFamily(TCEString devFamily)
Definition: AlmaIFIntegrator.cc:1125
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int secondPmemAddrw_
Definition: AlmaIFIntegrator.hh:148
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bool dmem_dram_
Definition: AlmaIFIntegrator.hh:155
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Definition: AlmaIFIntegrator.hh:153
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static const TCEString TTA_CORE_CLK
Definition: PlatformIntegrator.hh:303
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virtual void writeNewToplevel()
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int secondPmemDataw_
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int count() const
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Definition: Netlist.hh:63
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virtual bool createMemories(int coreId)
Definition: PlatformIntegrator.cc:542
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static std::string fileOfPath(const std::string pathName)
Definition: FileSystem.cc:101
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static std::string toString(const T &source)
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virtual size_t portCount() const
Definition: BaseNetlistBlock.cc:248
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Definition: HDLTemplateInstantiator.cc:89
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Definition: DummyMemGenerator.hh:43
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Definition: Netlist.cc:83
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Definition: Netlist.cc:238
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@ DRAM
Definition: MemoryGenerator.hh:63
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Definition: PlatformIntegrator.cc:179
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virtual void connectToplevelPort(const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")
Definition: PlatformIntegrator.cc:464
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int secondDmemDataw_
Definition: AlmaIFIntegrator.hh:145
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Definition: SignalGroup.hh:48
assert
#define assert(condition)
Definition: Application.hh:86
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Definition: FunctionUnit.hh:55
IDF::MachineImplementation::icDecoderParameterValue
std::string icDecoderParameterValue(const std::string &name) const
Definition: MachineImplementation.cc:1415
AlmaIFIntegrator.hh
AlmaIFIntegrator::findMemories
void findMemories()
Definition: AlmaIFIntegrator.cc:112
AlmaIFIntegrator::pmemInfo_
MemInfo pmemInfo_
Definition: AlmaIFIntegrator.hh:140
AlmaIFIntegrator::axiAddressWidth
TCEString axiAddressWidth() const
Definition: AlmaIFIntegrator.cc:237
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virtual MemoryGenerator & dmemInstance(MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition: AlmaIFIntegrator.cc:1016
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Definition: NetlistPortGroup.hh:53
SignalGroup.hh
HWOperation.hh
TTAMachine::HWOperation::name
const std::string & name() const
Definition: HWOperation.cc:141
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MemType type
Definition: MemoryGenerator.hh:68
InvalidData
Definition: Exception.hh:149
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ProGe::NetlistPort * resetPort() const
Definition: PlatformIntegrator.cc:704
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Definition: ProjectFileGenerator.hh:41
MemInfo::asAddrw
int asAddrw
Definition: MemoryGenerator.hh:72
Conversion.hh
AlmaIFIntegrator::broadcast_pmem_
bool broadcast_pmem_
Definition: AlmaIFIntegrator.hh:154
MemInfo::asName
TCEString asName
Definition: MemoryGenerator.hh:74
NetlistPort.hh
PlatformIntegrator::progeBlock
const ProGe::NetlistBlock & progeBlock() const
Definition: PlatformIntegrator.cc:530
AlmaIFIntegrator::axiSlavePortGroup
ProGe::NetlistPortGroup * axiSlavePortGroup()
Definition: AlmaIFIntegrator.cc:714
AlmaIFIntegrator::almaif_ttacore_ports
std::map< TCEString, ProGe::NetlistPort * > almaif_ttacore_ports
Definition: AlmaIFIntegrator.hh:131
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virtual FunctionUnitNavigator functionUnitNavigator() const
Definition: Machine.cc:380
AlmaIFIntegrator::imem_dp_
bool imem_dp_
Definition: AlmaIFIntegrator.hh:156
PlatformIntegrator::idf
const IDF::MachineImplementation * idf() const
Definition: PlatformIntegrator.cc:304
NetlistBlock.hh
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static void copy(const std::string &source, const std::string &target)
Definition: FileSystem.cc:524
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void addPort(NetlistPort &port)
Definition: NetlistPortGroup.cc:93
AlmaIFIntegrator::addPortToAlmaIFBlock
void addPortToAlmaIFBlock(const TCEString name, const TCEString width, const ProGe::Direction dir, const TCEString core_name="")
Definition: AlmaIFIntegrator.cc:679
AlmaIFIntegrator::dmemInfo_
MemInfo dmemInfo_
Definition: AlmaIFIntegrator.hh:140
TTAMachine::FunctionUnit::operationCount
virtual int operationCount() const
Definition: FunctionUnit.cc:419
DummyMemGenerator.hh
Environment.hh
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
Machine.hh
AlmaIFIntegrator::addPortToGroup
void addPortToGroup(ProGe::NetlistPortGroup *port_group, const ProGe::Direction dir, const TCEString name, const TCEString width)
Definition: AlmaIFIntegrator.cc:698
AlmaIFIntegrator::dmemHandled_
bool dmemHandled_
Definition: AlmaIFIntegrator.hh:143
PlatformIntegrator::machine
const TTAMachine::Machine * machine() const
Definition: PlatformIntegrator.cc:297
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void addLsu(TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition: MemoryGenerator.cc:376
AlmaIFIntegrator::deviceFamily_
TCEString deviceFamily_
Definition: AlmaIFIntegrator.hh:135
MemInfo::widthInMaus
int widthInMaus
Definition: MemoryGenerator.hh:70
AlmaIFIntegrator::pinTag
virtual TCEString pinTag() const
Definition: AlmaIFIntegrator.cc:1147
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Definition: VhdlRomGenerator.hh:42
PlatformIntegrator::imemInfo
const MemInfo & imemInfo() const
Definition: PlatformIntegrator.cc:651
ProGe::NetlistPort::name
std::string name() const
Definition: NetlistPort.cc:283
MemInfo::mauWidth
int mauWidth
Definition: MemoryGenerator.hh:69
AlmaIFIntegrator::connectCoreMemories
void connectCoreMemories(MemInfo mem, TCEString mem_name, TCEString mem_block_name, bool seconds)
Definition: AlmaIFIntegrator.cc:553
VhdlRomGenerator.hh
AlmaIFIntegrator::PMEM_NAME
static const TCEString PMEM_NAME
Definition: AlmaIFIntegrator.hh:121
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void addHdlFile(const TCEString &file)
Definition: ProjectFileGenerator.cc:56
AlmaIFIntegrator::exportUnconnectedPorts
void exportUnconnectedPorts(int coreId)
Definition: AlmaIFIntegrator.cc:969
AlmaIFIntegrator::addMemoryPorts
void addMemoryPorts(const TCEString as_name, int data_width, int addr_width, const bool isShared, const bool overrideAsWidth)
Definition: AlmaIFIntegrator.cc:778
AlmaIFIntegrator::addAlmaifFiles
void addAlmaifFiles()
Definition: AlmaIFIntegrator.cc:817
FileSystem::DIRECTORY_SEPARATOR
static const std::string DIRECTORY_SEPARATOR
Definition: FileSystem.hh:189
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
AlmaIFIntegrator::secondPmem_
bool secondPmem_
Definition: AlmaIFIntegrator.hh:142
NONE
@ NONE
Definition: MemoryGenerator.hh:59
AlmaIFIntegrator::AlmaIFIntegrator
AlmaIFIntegrator()
Definition: AlmaIFIntegrator.cc:61
DefaultProjectFileGenerator
Definition: DefaultProjectFileGenerator.hh:43
AlmaIFIntegrator::copyPlatformFile
void copyPlatformFile(const TCEString inputPath, std::vector< TCEString > &fileList, bool isScript=false) const
Definition: AlmaIFIntegrator.cc:877
MemInfo::isShared
bool isShared
Definition: MemoryGenerator.hh:73
PlatformIntegrator::integratorBlock
ProGe::NetlistBlock * integratorBlock()
Definition: PlatformIntegrator.cc:291
PlatformIntegrator::programName
TCEString programName() const
Definition: PlatformIntegrator.cc:133
MemType
MemType
Definition: MemoryGenerator.hh:57
HDLTemplateInstantiator::replacePlaceholder
void replacePlaceholder(const std::string &key, const std::string &replacer, bool append=false)
Definition: HDLTemplateInstantiator.cc:62
PlatformIntegrator::exportUnconnectedPorts
virtual void exportUnconnectedPorts(int coreId)
Definition: PlatformIntegrator.cc:453
ONCHIP
@ ONCHIP
Definition: MemoryGenerator.hh:61
PlatformIntegrator::progeFilePath
TCEString progeFilePath(TCEString fileName, bool absolute=false) const
Definition: PlatformIntegrator.cc:140
PlatformIntegrator::readLsuParameters
MemInfo readLsuParameters(const TTAMachine::FunctionUnit &lsu)
Definition: PlatformIntegrator.cc:403
AlmaIFIntegrator::imemGen_
MemoryGenerator * imemGen_
Definition: AlmaIFIntegrator.hh:129
false
find Finds info of the inner loops in the false
Definition: InnerLoopFinder.cc:81
AlmaIFIntegrator::DEFAULT_DEVICE
static const TCEString DEFAULT_DEVICE
Definition: AlmaIFIntegrator.hh:124
AlmaIFIntegrator::DEFAULT_RESERVED_PRIVATE_MEM_SIZE
static const int DEFAULT_RESERVED_PRIVATE_MEM_SIZE
Definition: AlmaIFIntegrator.hh:126
AlmaIFIntegrator::~AlmaIFIntegrator
virtual ~AlmaIFIntegrator()
Definition: AlmaIFIntegrator.cc:96
ProGe::DataType
DataType
Data types of hardware ports.
Definition: ProGeTypes.hh:46
AlmaIFIntegrator::initAlmaifBlock
void initAlmaifBlock()
Definition: AlmaIFIntegrator.cc:272
TCEString
Definition: TCEString.hh:53
PlatformIntegrator::warningStream
std::ostream & warningStream() const
Definition: PlatformIntegrator.cc:271
UNKNOWN
@ UNKNOWN
Definition: MemoryGenerator.hh:58
AlmaIFIntegrator::ALMAIF_MODULE
static const TCEString ALMAIF_MODULE
Definition: AlmaIFIntegrator.hh:123
TTAMachine::Machine::busNavigator
virtual BusNavigator busNavigator() const
Definition: Machine.cc:356
VHDL_ARRAY
@ VHDL_ARRAY
Definition: MemoryGenerator.hh:60
AlmaIFIntegrator::hasMinimalDebugger_
bool hasMinimalDebugger_
Definition: AlmaIFIntegrator.hh:151
ProGe::NetlistBlock::addPortGroup
void addPortGroup(NetlistPortGroup *portGroup)
Definition: BaseNetlistBlock.cc:508
ProGe::HDL
HDL
HDLs supported by ProGe.
Definition: ProGeTypes.hh:40
ProGe::NetlistPort
Definition: NetlistPort.hh:70
MathTools::roundUpToPowerTwo
static unsigned int roundUpToPowerTwo(unsigned int number)
AlmaIFIntegrator::dmemGen_
std::map< TCEString, MemoryGenerator * > dmemGen_
Definition: AlmaIFIntegrator.hh:130
AlmaIFIntegrator::integrateCore
virtual bool integrateCore(const ProGe::NetlistBlock &cores, int coreId)
Definition: AlmaIFIntegrator.cc:892
PlatformIntegrator
Definition: PlatformIntegrator.hh:65
AlmaIFIntegrator::almaifBlock_
ProGe::NetlistBlock * almaifBlock_
Definition: AlmaIFIntegrator.hh:133
TTAMachine::Machine::Navigator::item
ComponentType * item(int index) const
TTAMachine::FunctionUnit::operation
virtual HWOperation * operation(const std::string &name) const
Definition: FunctionUnit.cc:363
AlmaIFIntegrator::pmemHandled_
bool pmemHandled_
Definition: AlmaIFIntegrator.hh:143
AlmaIFIntegrator::projectFileGenerator
virtual ProjectFileGenerator * projectFileGenerator() const
Definition: AlmaIFIntegrator.cc:1152
PlatformIntegrator::outputFilePath
TCEString outputFilePath(TCEString fileName, bool absolute=false) const
Definition: PlatformIntegrator.cc:154
MathTools.hh
HDLTemplateInstantiator::instantiateTemplateFile
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
Definition: HDLTemplateInstantiator.cc:113
AlmaIFIntegrator::integrateProcessor
virtual void integrateProcessor(const ProGe::NetlistBlock *progeBlock)
Definition: AlmaIFIntegrator.cc:205
DS
#define DS
Definition: LLVMBackend.cc:124
MemInfo::portAddrw
int portAddrw
Definition: MemoryGenerator.hh:71
PlatformIntegrator::errorStream
std::ostream & errorStream() const
Definition: PlatformIntegrator.cc:278
PlatformIntegrator::addProGeFiles
void addProGeFiles() const
Definition: PlatformIntegrator.cc:640
AlmaIFIntegrator::imemInstance
virtual MemoryGenerator & imemInstance(MemInfo imem, int coreId)
Definition: AlmaIFIntegrator.cc:981
MathTools::requiredBits0Bit0
static int requiredBits0Bit0(long unsigned int number)
ProGe::Direction
Direction
Direction of the port.
Definition: ProGeTypes.hh:52
TTAMachine::Machine::Navigator
Definition: Machine.hh:186
AlmaIFIntegrator::fileGen_
DefaultProjectFileGenerator * fileGen_
Definition: AlmaIFIntegrator.hh:138
ProGe::NetlistBlock::port
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
Definition: NetlistBlock.cc:97
AlmaIFIntegrator::secondPmemName_
std::string secondPmemName_
Definition: AlmaIFIntegrator.hh:147
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
IDF::MachineImplementation
Definition: MachineImplementation.hh:54
MachineImplementation.hh
Environment::dataDirPath
static std::string dataDirPath(const std::string &prog)
Definition: Environment.cc:176
MemInfo::lsuName
TCEString lsuName
Definition: MemoryGenerator.hh:75
AlmaIFIntegrator::DMEM_NAME
static const TCEString DMEM_NAME
Definition: AlmaIFIntegrator.hh:120
TTAMachine::Machine
Definition: Machine.hh:73
AlmaIFIntegrator::targetClockFrequency
virtual int targetClockFrequency() const
Definition: AlmaIFIntegrator.cc:1142
MemoryGenerator
Definition: MemoryGenerator.hh:85
AlmaIFIntegrator::secondDmem_
bool secondDmem_
Definition: AlmaIFIntegrator.hh:142